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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-05 09:38:38 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-05 10:47:41 +0200 |
| commit | dfb71344973b5327611432e7b33429f73f0bd03c (patch) | |
| tree | 3d135e2a9cd80c63bc335e346799388d202be42b /testsuite/gna/issue1708/ex3.vhdl | |
| parent | 587497a48febf62e5c44d97796e78136c29d6d0c (diff) | |
| download | ghdl-dfb71344973b5327611432e7b33429f73f0bd03c.tar.gz ghdl-dfb71344973b5327611432e7b33429f73f0bd03c.tar.bz2 ghdl-dfb71344973b5327611432e7b33429f73f0bd03c.zip | |
testsuite/gna: add more tests for #1708
Diffstat (limited to 'testsuite/gna/issue1708/ex3.vhdl')
| -rw-r--r-- | testsuite/gna/issue1708/ex3.vhdl | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/testsuite/gna/issue1708/ex3.vhdl b/testsuite/gna/issue1708/ex3.vhdl new file mode 100644 index 000000000..ea245aeb1 --- /dev/null +++ b/testsuite/gna/issue1708/ex3.vhdl @@ -0,0 +1,33 @@ +Library ieee; +use ieee.std_logic_1164.all; + +entity ex3 is +end entity; + + +architecture tb of ex3 is + + signal a,b : std_logic := '0'; + signal clk_sys : std_logic; + + default clock is rising_edge(clk_sys); +begin + + gen_clock_proc : process + begin + clk_sys <= '1'; + wait for 5 ns; + clk_sys <= '0'; + wait for 5 ns; + end process; + + test_proc : process + begin + a <= '1'; + wait for 50 ns; + std.env.finish; + end process; + + my_seq : assert never {a = '1'}[->3]; + +end architecture tb; |