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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-02 15:45:10 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-02 15:45:41 +0100 |
| commit | dc7c0850feb2f8200ce552601ebd467cd0a99b9f (patch) | |
| tree | 5a8711f10f7b28c02b64c5cec1965b5bb7f9d49c /testsuite/gna/issue1120/repro2.vhdl | |
| parent | a87153e498853d35eb7b1fb0360b8313f54ffb0a (diff) | |
| download | ghdl-dc7c0850feb2f8200ce552601ebd467cd0a99b9f.tar.gz ghdl-dc7c0850feb2f8200ce552601ebd467cd0a99b9f.tar.bz2 ghdl-dc7c0850feb2f8200ce552601ebd467cd0a99b9f.zip | |
testsuite/gna: add test for #1120
Diffstat (limited to 'testsuite/gna/issue1120/repro2.vhdl')
| -rw-r--r-- | testsuite/gna/issue1120/repro2.vhdl | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/gna/issue1120/repro2.vhdl b/testsuite/gna/issue1120/repro2.vhdl new file mode 100644 index 000000000..915b66ba4 --- /dev/null +++ b/testsuite/gna/issue1120/repro2.vhdl @@ -0,0 +1,19 @@ +entity repro2 is + generic( + BITS : positive := 4); + port( + min : in bit_vector(BITS - 1 downto 0) := "1010"); +end entity; + +architecture rtl of repro2 is +begin + process + variable sum : bit_vector(BITS - 2 downto 0); + variable carry : bit; + begin + (carry, sum) := min; + assert carry = '1'; + assert sum = "010"; + wait; + end process; +end architecture; |