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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-18 20:04:39 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-12-21 07:36:46 +0100 |
| commit | 6e63d78e54e243b864bacf376c481760362b0825 (patch) | |
| tree | 1d1076b43673cc4b995e99ae2fe7d9219aac68de /src | |
| parent | 0836f191563eae6cd5ada9dbc2b8a871a522bc5c (diff) | |
| download | ghdl-6e63d78e54e243b864bacf376c481760362b0825.tar.gz ghdl-6e63d78e54e243b864bacf376c481760362b0825.tar.bz2 ghdl-6e63d78e54e243b864bacf376c481760362b0825.zip | |
simul: minor refactoring.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index c1bc7ff88..4396bb9cd 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1246,13 +1246,11 @@ package body Simul.Elaboration is Assoc : Iir_Association_Element_By_Expression; Inter : Iir) is - Formal : Iir; - Actual : Iir; + Formal : constant Iir := Get_Association_Formal (Assoc, Inter); + Actual : constant Iir := Get_Actual (Assoc); Local_Expr : Iir_Value_Literal_Acc; Formal_Expr : Iir_Value_Literal_Acc; begin - Formal := Get_Association_Formal (Assoc, Inter); - Actual := Get_Actual (Assoc); Formal_Expr := Execute_Name (Formal_Instance, Formal, True); Formal_Expr := Unshare_Bounds (Formal_Expr, Global_Pool'Access); if Actual_Expr = null then |