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| author | Tristan Gingold <tgingold@free.fr> | 2017-12-05 18:38:56 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-12-05 18:38:56 +0100 |
| commit | 56fe3ce790d838b530ef4ecdcdb4ae6b6097f1d0 (patch) | |
| tree | ab000076fc4dc364e388c27caff92bdf912dae2f /src | |
| parent | 83f07243e90f7fd60516738f42a79d9f7cc01736 (diff) | |
| download | ghdl-56fe3ce790d838b530ef4ecdcdb4ae6b6097f1d0.tar.gz ghdl-56fe3ce790d838b530ef4ecdcdb4ae6b6097f1d0.tar.bz2 ghdl-56fe3ce790d838b530ef4ecdcdb4ae6b6097f1d0.zip | |
simul: fix choice list for case generate statement.
Diffstat (limited to 'src')
| -rw-r--r-- | src/vhdl/simulate/simul-annotations.adb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 4c6e6e80b..eac35f50f 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -906,8 +906,10 @@ package body Simul.Annotations is begin Assoc := Get_Case_Statement_Alternative_Chain (Stmt); while Assoc /= Null_Iir loop - Annotate_Generate_Statement_Body - (Block_Info, Get_Associated_Block (Assoc), Null_Iir); + if not Get_Same_Alternative_Flag (Assoc) then + Annotate_Generate_Statement_Body + (Block_Info, Get_Associated_Block (Assoc), Null_Iir); + end if; Assoc := Get_Chain (Assoc); end loop; end Annotate_Case_Generate_Statement; |