From 56fe3ce790d838b530ef4ecdcdb4ae6b6097f1d0 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Tue, 5 Dec 2017 18:38:56 +0100 Subject: simul: fix choice list for case generate statement. --- src/vhdl/simulate/simul-annotations.adb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 4c6e6e80b..eac35f50f 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -906,8 +906,10 @@ package body Simul.Annotations is begin Assoc := Get_Case_Statement_Alternative_Chain (Stmt); while Assoc /= Null_Iir loop - Annotate_Generate_Statement_Body - (Block_Info, Get_Associated_Block (Assoc), Null_Iir); + if not Get_Same_Alternative_Flag (Assoc) then + Annotate_Generate_Statement_Body + (Block_Info, Get_Associated_Block (Assoc), Null_Iir); + end if; Assoc := Get_Chain (Assoc); end loop; end Annotate_Case_Generate_Statement; -- cgit v1.2.3