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| author | Tristan Gingold <tgingold@free.fr> | 2020-05-27 08:00:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-05-27 08:00:42 +0200 |
| commit | 67f926fc1323c375d14fee36a092e39a92d505dd (patch) | |
| tree | 2721ed6d11218bd9db3358e913d08f874dc9bc6a /src/vhdl/vhdl-nodes.ads | |
| parent | defe3b033f1c3026312c94e5ce661172c670e9a5 (diff) | |
| download | ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.tar.gz ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.tar.bz2 ghdl-67f926fc1323c375d14fee36a092e39a92d505dd.zip | |
synth: handle reduction operators. Fix #1342
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 2460e7bfc..8f3c003fa 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5471,8 +5471,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Falling_Edge, -- VHDL-2008 unary logic operators - Iir_Predefined_Ieee_1164_Vector_And_Reduce, - Iir_Predefined_Ieee_1164_Vector_Or_Reduce, + Iir_Predefined_Ieee_1164_And_Suv, + Iir_Predefined_Ieee_1164_Nand_Suv, + Iir_Predefined_Ieee_1164_Or_Suv, + Iir_Predefined_Ieee_1164_Nor_Suv, + Iir_Predefined_Ieee_1164_Xor_Suv, + Iir_Predefined_Ieee_1164_Xnor_Suv, Iir_Predefined_Ieee_1164_Vector_Sll, Iir_Predefined_Ieee_1164_Vector_Srl, |