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| author | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:21:24 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-10-11 06:21:24 +0200 |
| commit | 2714a30c3753c76cda95eb994851a8be95e60ad9 (patch) | |
| tree | ed759d92892d21a21cc5e60e2995e9feef5ed1a2 /src/vhdl/vhdl-nodes.ads | |
| parent | f4be996776af67b5242e9ec5fc18ec1fe27d0efb (diff) | |
| download | ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.tar.gz ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.tar.bz2 ghdl-2714a30c3753c76cda95eb994851a8be95e60ad9.zip | |
vhdl: recognize minus from std_logic_unsigned
Diffstat (limited to 'src/vhdl/vhdl-nodes.ads')
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 840f0bb70..f903a4c4d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5063,6 +5063,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv, + Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Slv, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Lt_Int_Slv, |