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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-24 07:34:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-24 07:34:07 +0200 |
| commit | 04a1fcc6b83e9e50849b05b629d6c8eb81143d38 (patch) | |
| tree | ade0900933dc93bda7fb8828ce574759f037c518 /src/synth | |
| parent | 84516bdbe86290f475ad177371975991d38d065c (diff) | |
| download | ghdl-04a1fcc6b83e9e50849b05b629d6c8eb81143d38.tar.gz ghdl-04a1fcc6b83e9e50849b05b629d6c8eb81143d38.tar.bz2 ghdl-04a1fcc6b83e9e50849b05b629d6c8eb81143d38.zip | |
elab-vhdl_values-debug: slightly improve output
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/elab-vhdl_values-debug.adb | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb index 2faf45b7b..227764734 100644 --- a/src/synth/elab-vhdl_values-debug.adb +++ b/src/synth/elab-vhdl_values-debug.adb @@ -60,8 +60,10 @@ package body Elab.Vhdl_Values.Debug is procedure Debug_Typ1 (T : Type_Acc) is begin case T.Kind is - when Type_Bit - | Type_Logic => + when Type_Bit => + Put ("bit"); + Debug_Typ_Phys (T); + when Type_Logic => Put ("bit/logic"); Debug_Typ_Phys (T); when Type_Vector => @@ -292,6 +294,8 @@ package body Elab.Vhdl_Values.Debug is New_Line; when Value_Signal => Put ("signal "); + Put_Uns32 (Uns32 (V.Val.S)); + Put (": "); Debug_Typ1 (V.Typ); New_Line; when Value_Wire => |