From 04a1fcc6b83e9e50849b05b629d6c8eb81143d38 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Tue, 24 May 2022 07:34:07 +0200
Subject: elab-vhdl_values-debug: slightly improve output

---
 src/synth/elab-vhdl_values-debug.adb | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src/synth')

diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb
index 2faf45b7b..227764734 100644
--- a/src/synth/elab-vhdl_values-debug.adb
+++ b/src/synth/elab-vhdl_values-debug.adb
@@ -60,8 +60,10 @@ package body Elab.Vhdl_Values.Debug is
    procedure Debug_Typ1 (T : Type_Acc) is
    begin
       case T.Kind is
-         when Type_Bit
-           | Type_Logic =>
+         when Type_Bit =>
+            Put ("bit");
+            Debug_Typ_Phys (T);
+         when Type_Logic =>
             Put ("bit/logic");
             Debug_Typ_Phys (T);
          when Type_Vector =>
@@ -292,6 +294,8 @@ package body Elab.Vhdl_Values.Debug is
             New_Line;
          when Value_Signal =>
             Put ("signal ");
+            Put_Uns32 (Uns32 (V.Val.S));
+            Put (": ");
             Debug_Typ1 (V.Typ);
             New_Line;
          when Value_Wire =>
-- 
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