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author | Tristan Gingold <tgingold@free.fr> | 2023-02-09 07:53:57 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-02-09 07:53:57 +0100 |
commit | d1ff79789a621a485aeb4c854ce136c9f6a8ff70 (patch) | |
tree | 23a7ce595c0b7e3e025583ed8dcadd9e91f669cc /src/synth/synth-ieee-std_logic_arith.adb | |
parent | 7a0759479a991ab9ec1e2716f34b738a0286fa9a (diff) | |
download | ghdl-d1ff79789a621a485aeb4c854ce136c9f6a8ff70.tar.gz ghdl-d1ff79789a621a485aeb4c854ce136c9f6a8ff70.tar.bz2 ghdl-d1ff79789a621a485aeb4c854ce136c9f6a8ff70.zip |
synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vector
Fix #2347
Diffstat (limited to 'src/synth/synth-ieee-std_logic_arith.adb')
-rw-r--r-- | src/synth/synth-ieee-std_logic_arith.adb | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/synth/synth-ieee-std_logic_arith.adb b/src/synth/synth-ieee-std_logic_arith.adb index befb217d0..1cc68d2f8 100644 --- a/src/synth/synth-ieee-std_logic_arith.adb +++ b/src/synth/synth-ieee-std_logic_arith.adb @@ -519,4 +519,34 @@ package body Synth.Ieee.Std_Logic_Arith is return Compare_Vec (L.Mem, Rmem, Len, Rlen, True, True); end Compare_Sgn_Int; + function Conv_Slv (Arg : Memtyp; + Size : Uns32; + Signed : Boolean; + Loc : Location_Type) return Memtyp + is + Alen : constant Uns32 := Arg.Typ.Abound.Len; + Res : Memtyp; + V : Sl_X01; + begin + Res.Typ := Create_Res_Type (Arg.Typ, Size); + Res := Create_Memory (Res.Typ); + V := '0'; + for I in 1 .. Size loop + if I <= Alen then + V := Sl_To_X01 (Read_Std_Logic (Arg.Mem, Alen - I)); + if V = 'X' then + Warn_X (Loc); + Fill (Res.Mem, Size, 'X'); + return Res; + end if; + else + if not Signed then + V := '0'; + end if; + end if; + Write_Std_Logic (Res.Mem, Size - I, V); + end loop; + return Res; + end Conv_Slv; + end Synth.Ieee.Std_Logic_Arith; |