synth-vhdl_eval: handle std_logic_arith.conv_std_logic_vector

Fix #2347

3 files changed, 43 insertions, 0 deletions

diff --git a/src/synth/synth-ieee-std_logic_arith.adb b/src/synth/synth-ieee-std_logic_arith.adb
index befb217d0..1cc68d2f8 100644
--- a/src/synth/synth-ieee-std_logic_arith.adb
+++ b/src/synth/synth-ieee-std_logic_arith.adb
@@ -519,4 +519,34 @@ package body Synth.Ieee.Std_Logic_Arith is
       return Compare_Vec (L.Mem, Rmem, Len, Rlen, True, True);
    end Compare_Sgn_Int;
 
+   function Conv_Slv (Arg : Memtyp;
+                      Size : Uns32;
+                      Signed : Boolean;
+                      Loc : Location_Type) return Memtyp
+   is
+      Alen : constant Uns32 := Arg.Typ.Abound.Len;
+      Res : Memtyp;
+      V : Sl_X01;
+   begin
+      Res.Typ := Create_Res_Type (Arg.Typ, Size);
+      Res := Create_Memory (Res.Typ);
+      V := '0';
+      for I in 1 .. Size loop
+         if I <= Alen then
+            V := Sl_To_X01 (Read_Std_Logic (Arg.Mem, Alen - I));
+            if V = 'X' then
+               Warn_X (Loc);
+               Fill (Res.Mem, Size, 'X');
+               return Res;
+            end if;
+         else
+            if not Signed then
+               V := '0';
+            end if;
+         end if;
+         Write_Std_Logic (Res.Mem, Size - I, V);
+      end loop;
+      return Res;
+   end Conv_Slv;
+
 end Synth.Ieee.Std_Logic_Arith;
diff --git a/src/synth/synth-ieee-std_logic_arith.ads b/src/synth/synth-ieee-std_logic_arith.ads
index 0c8d400f0..c4956c320 100644
--- a/src/synth/synth-ieee-std_logic_arith.ads
+++ b/src/synth/synth-ieee-std_logic_arith.ads
@@ -67,4 +67,10 @@ package Synth.Ieee.Std_Logic_Arith is
    function Compare_Sgn_Int (L : Memtyp; R : Int64; Loc : Location_Type)
                             return Order_Type;
 
+   --  Conversion from signed/unsigned to std_logic_vector.
+   function Conv_Slv (Arg : Memtyp;
+                      Size : Uns32;
+                      Signed : Boolean;
+                      Loc : Location_Type) return Memtyp;
+
 end Synth.Ieee.Std_Logic_Arith;
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb
index 2cc70bd52..020c67896 100644
--- a/src/synth/synth-vhdl_eval.adb
+++ b/src/synth/synth-vhdl_eval.adb
@@ -2710,6 +2710,13 @@ package body Synth.Vhdl_Eval is
                return Resize_Vec (Param1, Uns32 (Len), True);
             end;
 
+         when Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn =>
+            return Conv_Slv
+              (Param1, Uns32 (Read_Discrete (Param2)), True, +Expr);
+         when Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns =>
+            return Conv_Slv
+              (Param1, Uns32 (Read_Discrete (Param2)), False, +Expr);
+
          when Iir_Predefined_Ieee_1164_To_Stdulogic =>
             declare
                B : Std_Ulogic;