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author | Tristan Gingold <tgingold@free.fr> | 2023-01-31 18:57:14 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-31 20:27:01 +0100 |
commit | 919cc95cce51bbe0fb1fb0778ed63fffd184977b (patch) | |
tree | 6aaee65fb0ca7b73adbdb999b8fc32a61046969a /src/simul/simul-vhdl_debug.adb | |
parent | eaf29d1c2491419a0e9b51e2866c329f60892613 (diff) | |
download | ghdl-919cc95cce51bbe0fb1fb0778ed63fffd184977b.tar.gz ghdl-919cc95cce51bbe0fb1fb0778ed63fffd184977b.tar.bz2 ghdl-919cc95cce51bbe0fb1fb0778ed63fffd184977b.zip |
ghdlsimul: extract simul-main from simul-vhdl_simul
Diffstat (limited to 'src/simul/simul-vhdl_debug.adb')
-rw-r--r-- | src/simul/simul-vhdl_debug.adb | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_debug.adb b/src/simul/simul-vhdl_debug.adb index 6ae5976ff..0d94be076 100644 --- a/src/simul/simul-vhdl_debug.adb +++ b/src/simul/simul-vhdl_debug.adb @@ -38,6 +38,7 @@ with Elab.Vhdl_Values; use Elab.Vhdl_Values; with Elab.Vhdl_Values.Debug; use Elab.Vhdl_Values.Debug; with Simul.Vhdl_Elab; use Simul.Vhdl_Elab; with Simul.Vhdl_Simul; +with Simul.Main; with Grt.Types; use Grt.Types; with Grt.Vhdl_Types; use Grt.Vhdl_Types; @@ -788,14 +789,14 @@ package body Simul.Vhdl_Debug is if P <= Line'Last then L := Get_Word (Line, P); if Line (P .. L) = "-s" then - Simul.Vhdl_Simul.Break_Step := True; + Simul.Main.Break_Step := True; else Delta_Time := Grt.Options.Parse_Time (Line (P .. L)); if Delta_Time = -1 then -- Error, ignore command. return; end if; - Simul.Vhdl_Simul.Break_Time := Current_Time + Delta_Time; + Simul.Main.Break_Time := Current_Time + Delta_Time; Grt.Processes.Next_Time := Current_Time + Delta_Time; end if; end if; |