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authorTristan Gingold <tgingold@free.fr>2020-05-17 09:45:00 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-17 09:45:00 +0200
commitf01c93b00c618e994f795285a5eb3debeaf03fcf (patch)
tree309bb20ae936e3fd4fc050dbd47a61483d2bde7a
parent291fde96273b8b2b6520b7834ff5a9d9623a48f4 (diff)
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testsuite/synth: add a test for #1317
-rw-r--r--testsuite/synth/issue1317/repro.vhdl24
-rwxr-xr-xtestsuite/synth/issue1317/testsuite.sh7
2 files changed, 31 insertions, 0 deletions
diff --git a/testsuite/synth/issue1317/repro.vhdl b/testsuite/synth/issue1317/repro.vhdl
new file mode 100644
index 000000000..21d28c470
--- /dev/null
+++ b/testsuite/synth/issue1317/repro.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity simple01 is
+ port (a, b, c : in std_logic;
+ z : out std_logic);
+end simple01;
+
+architecture behav of simple01 is
+begin
+ process(A, B, C)
+ variable temp : std_logic;
+ begin
+ case a is
+ when '1' =>
+ assert b = '0';
+ z <= '0';
+ when '0' =>
+ z <= '1';
+ when others =>
+ z <= 'X';
+ end case;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1317/testsuite.sh b/testsuite/synth/issue1317/testsuite.sh
new file mode 100755
index 000000000..e9dc72228
--- /dev/null
+++ b/testsuite/synth/issue1317/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only repro
+
+echo "Test successful"