From 774dcd646151328991440b7b7c2cbaf750dcc2b6 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 6 Jul 2022 22:38:50 +0200 Subject: netlists-disp_verilog: fix output for id_abs. For #2123 --- src/synth/netlists-disp_verilog.adb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 7d1354403..950f6fd36 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -854,7 +854,8 @@ package body Netlists.Disp_Verilog is when Id_Neg => Disp_Template (" assign \o0 = -\i0;" & NL, Inst); when Id_Abs=> - Disp_Template (" \o0 <= \si0 >= 0 ? \i0 : -\i0;" & NL, Inst); + Disp_Template (" assign \o0 = \si0 >= 0 ? \i0 : -\i0;" & NL, + Inst); when Id_Extract => Disp_Template (" assign \o0 = ", Inst); Disp_Extract (Inst); -- cgit v1.2.3