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-rw-r--r--testsuite/synth/issue2143/repro2.vhdl22
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue2143/repro2.vhdl b/testsuite/synth/issue2143/repro2.vhdl
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--- /dev/null
+++ b/testsuite/synth/issue2143/repro2.vhdl
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+entity repro2 is
+ port (clk : bit;
+ o : out bit);
+end;
+
+architecture struct of repro2 is
+ type entry_t is record
+ a : bit;
+ end record;
+
+ type table_t is array (natural range<>, natural range<>) of entry_t;
+
+ function fun return table_t is
+ variable ret : table_t(0 to 7, 0 to 7);
+ begin
+ return ret;
+ end function;
+
+ constant table : table_t := fun;
+begin
+ o <= table(0,0).a when clk = '1' else '0';
+end architecture;