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| author | Sam McNally <sammc@chromium.org> | 2021-03-11 11:41:46 +1100 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2021-03-11 23:25:04 +0000 |
| commit | 80591575f7abedcf13f05f39af621404bfe96e08 (patch) | |
| tree | efb1f275719fcc9d4d0099249fe6472b49976bc0 | |
| parent | c60eceff19020ac8ddb048ef6fc49efe034bb5ef (diff) | |
| download | flashrom-80591575f7abedcf13f05f39af621404bfe96e08.tar.gz flashrom-80591575f7abedcf13f05f39af621404bfe96e08.tar.bz2 flashrom-80591575f7abedcf13f05f39af621404bfe96e08.zip | |
chipset_enable.c: Add PCI ID for Comet Lake U Base
TEST=`flashrom -r` on a kindred chromebook with a Celeron 5205U.
Change-Id: I627dcacdad167343287ac0ec26b47505c2f823ee
Signed-off-by: Sam McNally <sammc@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/51401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
| -rw-r--r-- | chipset_enable.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chipset_enable.c b/chipset_enable.c index 138cb12c..d5c10c42 100644 --- a/chipset_enable.c +++ b/chipset_enable.c @@ -2020,6 +2020,7 @@ const struct penable chipset_enables[] = { {0x8086, 0x9d58, B_S, NT, "Intel", "Kaby Lake U Premium", enable_flash_pch100}, {0x8086, 0x9d84, B_S, DEP, "Intel", "Cannon Lake U Premium", enable_flash_pch300}, {0x8086, 0x0284, B_S, DEP, "Intel", "Comet Lake U Premium", enable_flash_pch400}, + {0x8086, 0x0285, B_S, DEP, "Intel", "Comet Lake U Base", enable_flash_pch400}, {0x8086, 0xa141, B_S, NT, "Intel", "Sunrise Point Desktop Sample", enable_flash_pch100}, {0x8086, 0xa142, B_S, NT, "Intel", "Sunrise Point Unknown Sample", enable_flash_pch100}, {0x8086, 0xa143, B_S, DEP, "Intel", "H110", enable_flash_pch100}, |