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author | Tim Chen <tim-chen@quanta.corp-partner.google.com> | 2020-07-06 14:59:21 +0800 |
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committer | Edward O'Callaghan <quasisec@chromium.org> | 2021-03-11 00:31:38 +0000 |
commit | c60eceff19020ac8ddb048ef6fc49efe034bb5ef (patch) | |
tree | ee5e55411861284e7d6f6cf53267d58f3689b371 | |
parent | 9635cb4d9115dc5abac36ea77a443714f045beb6 (diff) | |
download | flashrom-c60eceff19020ac8ddb048ef6fc49efe034bb5ef.tar.gz flashrom-c60eceff19020ac8ddb048ef6fc49efe034bb5ef.tar.bz2 flashrom-c60eceff19020ac8ddb048ef6fc49efe034bb5ef.zip |
CHROMIUM: flashrom: update .tested field for EN25QH128
update .tested field from TEST_UNTESTED to TEST_OK_PREW
BUG=b:159768722
BRANCH=none
TEST=Flash Duffy bios
pass on running `flashrom_tester /usr/sbin/flashrom host`
Original-Change-Id: I9467588988c2cab0987737c53ace0832144ef169
Original-Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Commit-Queue: Edward O'Callaghan <quasisec@chromium.org>
(cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff)
Change-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
-rw-r--r-- | flashchips.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/flashchips.c b/flashchips.c index 4aaa8ac4..d47871db 100644 --- a/flashchips.c +++ b/flashchips.c @@ -5105,7 +5105,7 @@ const struct flashchip flashchips[] = { /* OTP: 512B total; enter 0x3A */ /* QPI enable 0x38, disable 0xFF */ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, - .tested = TEST_UNTESTED, + .tested = TEST_OK_PREW, .probe = probe_spi_rdid, .probe_timing = TIMING_ZERO, .block_erasers = |