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-rw-r--r--fpga/hp_lcd_driver/Makefile2
-rw-r--r--fpga/hp_lcd_driver/clkgen_zynq7.vhdl4
-rw-r--r--fpga/hp_lcd_driver/common.vhdl38
-rw-r--r--fpga/hp_lcd_driver/fb_hw.vhdl305
-rw-r--r--fpga/hp_lcd_driver/hp_lcd_driver.vhdl12
-rw-r--r--fpga/hp_lcd_driver/kbd_uarts.vhdl456
-rw-r--r--fpga/hp_lcd_driver/output_stage.vhdl2
-rw-r--r--fpga/hp_lcd_driver/tmds_encode.vhdl2
-rw-r--r--fpga/hp_lcd_driver/tmds_output_artix7.vhdl2
-rw-r--r--fpga/hp_lcd_driver/tmds_phy_artix7.vhdl12
-rw-r--r--fpga/hp_lcd_driver/vnc_hw.vhdl10
-rw-r--r--fpga/hp_lcd_driver/vnc_serializer.vhdl24
-rw-r--r--fpga/hp_lcd_driver/vram_artix7.vhdl2
-rw-r--r--fpga/hp_lcd_driver/zynq7.mk1
-rw-r--r--fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl1
-rw-r--r--fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl44
-rw-r--r--fpga/hp_lcd_driver/zynq7_ip/axi_protocol_converter_0.tcl25
-rw-r--r--fpga/hp_lcd_driver/zynq7_wrapper.vhdl529
18 files changed, 783 insertions, 688 deletions
diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 6e21f21..0558bdd 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -7,7 +7,7 @@ TARGETS=ebaz4205
better_default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
scp build_ebaz4205/out/hp_lcd_driver.bin ${DIP}:/boot/uboot/hp_lcd_driver.bin
- #ssh -n ${DIP} reboot < /dev/null &
+ ssh -n ${DIP} reboot < /dev/null &
qbetter_default: build_rando_a7/hp_lcd_driver.svf
./prog_a7
diff --git a/fpga/hp_lcd_driver/clkgen_zynq7.vhdl b/fpga/hp_lcd_driver/clkgen_zynq7.vhdl
index e60c1b1..4c5677a 100644
--- a/fpga/hp_lcd_driver/clkgen_zynq7.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_zynq7.vhdl
@@ -22,8 +22,8 @@ architecture Behavioural of clkgen is
signal clk_260m : std_logic;
signal clk_78_571m : std_logic;
signal clk_26m : std_logic;
- signal clk_52m_o : std_logic;
- signal clk_52m_i : std_logic;
+ signal clk_52m_o : std_logic;
+ signal clk_52m_i : std_logic;
signal reset : std_logic;
begin
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl
index a3e41d4..cfe3143 100644
--- a/fpga/hp_lcd_driver/common.vhdl
+++ b/fpga/hp_lcd_driver/common.vhdl
@@ -44,12 +44,12 @@ entity common is
video_out_valid : out std_logic;
video_out_clk : out std_logic;
video_out_index : out std_logic;
- video_in_addr : out std_logic_vector(addr_width-1 downto 0);
- video_in_clk : out std_logic;
- video_in_gate : in std_logic;
- video_in_r : in std_logic_vector(7 downto 0);
- video_in_g : in std_logic_vector(7 downto 0);
- video_in_b : in std_logic_vector(7 downto 0)
+ video_in_addr : out std_logic_vector(addr_width-1 downto 0);
+ video_in_clk : out std_logic;
+ video_in_gate : in std_logic;
+ video_in_r : in std_logic_vector(7 downto 0);
+ video_in_g : in std_logic_vector(7 downto 0);
+ video_in_b : in std_logic_vector(7 downto 0)
);
end common;
@@ -65,9 +65,9 @@ architecture Behavioral of common is
signal rd_addr : std_logic_vector(addr_width-1 downto 0);
signal rd_data : std_logic_vector(video_width-1 downto 0);
- signal r : std_logic_vector(7 downto 0);
- signal g : std_logic_vector(7 downto 0);
- signal b : std_logic_vector(7 downto 0);
+ signal r : std_logic_vector(7 downto 0);
+ signal g : std_logic_vector(7 downto 0);
+ signal b : std_logic_vector(7 downto 0);
signal r_s : std_logic_vector(7 downto 0);
signal g_s : std_logic_vector(7 downto 0);
signal b_s : std_logic_vector(7 downto 0);
@@ -251,28 +251,28 @@ begin
rd_data => rd_data
);
- video_in_addr <= rd_addr;
- video_in_clk <= o_clk;
+ video_in_addr <= rd_addr;
+ video_in_clk <= o_clk;
r_s <= x"ff" when rd_data(0) = '1' else
- x"00";
+ x"00";
g_s <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else
- x"80" when rd_data(1) = '1' else
- x"00";
+ x"80" when rd_data(1) = '1' else
+ x"00";
b_s <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else
- x"80" when rd_data(2) = '1' else
- x"00";
+ x"80" when rd_data(2) = '1' else
+ x"00";
r <= r_s when video_in_gate = '0' else
- video_in_r;
+ video_in_r;
g <= g_s when video_in_gate = '0' else
- video_in_g;
+ video_in_g;
b <= b_s when video_in_gate = '0' else
- video_in_b;
+ video_in_b;
output0 : entity work.output_stage
diff --git a/fpga/hp_lcd_driver/fb_hw.vhdl b/fpga/hp_lcd_driver/fb_hw.vhdl
index 9d12ae1..d3e20a5 100644
--- a/fpga/hp_lcd_driver/fb_hw.vhdl
+++ b/fpga/hp_lcd_driver/fb_hw.vhdl
@@ -8,173 +8,174 @@ entity fb_hw is
addr_width : integer := 17
);
port (
- s_axi_aclk : in STD_LOGIC;
- s_axi_aresetn : in STD_LOGIC;
- s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_awlock : in STD_LOGIC_VECTOR(1 downto 0);
- s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awvalid : in STD_LOGIC;
- s_axi_awready : out STD_LOGIC;
- s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_wlast : in STD_LOGIC;
- s_axi_wvalid : in STD_LOGIC;
- s_axi_wready : out STD_LOGIC;
- s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_bvalid : out STD_LOGIC;
- s_axi_bready : in STD_LOGIC;
- s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_arlock : in STD_LOGIC_VECTOR( 1 downto 0);
- s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_arvalid : in STD_LOGIC;
- s_axi_arready : out STD_LOGIC;
- s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_rlast : out STD_LOGIC;
- s_axi_rvalid : out STD_LOGIC;
- s_axi_rready : in STD_LOGIC;
-
- overlay_clk : in std_logic;
- overlay_addr : in std_logic_vector(addr_width-1 downto 0);
- overlay_gate : out std_logic;
- overlay_r : out std_logic_vector(7 downto 0);
- overlay_g : out std_logic_vector(7 downto 0);
- overlay_b : out std_logic_vector(7 downto 0)
-
-
-
-);
+ s_axi_aclk : in std_logic;
+ s_axi_aresetn : in std_logic;
+ s_axi_awid : in std_logic_vector (11 downto 0);
+ s_axi_awaddr : in std_logic_vector (31 downto 0);
+ s_axi_awlen : in std_logic_vector (3 downto 0);
+ s_axi_awsize : in std_logic_vector (2 downto 0);
+ s_axi_awburst : in std_logic_vector (1 downto 0);
+ s_axi_awlock : in std_logic_vector(1 downto 0);
+ s_axi_awcache : in std_logic_vector (3 downto 0);
+ s_axi_awprot : in std_logic_vector (2 downto 0);
+ s_axi_awvalid : in std_logic;
+ s_axi_awready : out std_logic;
+ s_axi_wdata : in std_logic_vector (31 downto 0);
+ s_axi_wstrb : in std_logic_vector (3 downto 0);
+ s_axi_wlast : in std_logic;
+ s_axi_wvalid : in std_logic;
+ s_axi_wready : out std_logic;
+ s_axi_bid : out std_logic_vector (11 downto 0);
+ s_axi_bresp : out std_logic_vector (1 downto 0);
+ s_axi_bvalid : out std_logic;
+ s_axi_bready : in std_logic;
+ s_axi_arid : in std_logic_vector (11 downto 0);
+ s_axi_araddr : in std_logic_vector (31 downto 0);
+ s_axi_arlen : in std_logic_vector (3 downto 0);
+ s_axi_arsize : in std_logic_vector (2 downto 0);
+ s_axi_arburst : in std_logic_vector (1 downto 0);
+ s_axi_arlock : in std_logic_vector(1 downto 0);
+ s_axi_arcache : in std_logic_vector (3 downto 0);
+ s_axi_arprot : in std_logic_vector (2 downto 0);
+ s_axi_arvalid : in std_logic;
+ s_axi_arready : out std_logic;
+ s_axi_rid : out std_logic_vector (11 downto 0);
+ s_axi_rdata : out std_logic_vector (31 downto 0);
+ s_axi_rresp : out std_logic_vector (1 downto 0);
+ s_axi_rlast : out std_logic;
+ s_axi_rvalid : out std_logic;
+ s_axi_rready : in std_logic;
+
+ overlay_clk : in std_logic;
+ overlay_addr : in std_logic_vector(addr_width-1 downto 0);
+ overlay_gate : out std_logic;
+ overlay_r : out std_logic_vector(7 downto 0);
+ overlay_g : out std_logic_vector(7 downto 0);
+ overlay_b : out std_logic_vector(7 downto 0)
+
+
+
+ );
end fb_hw;
architecture Behavioural of fb_hw is
- type t_palette is array (0 to 15) of std_logic_vector(7 downto 0);
+ type t_palette is array (0 to 15) of std_logic_vector(7 downto 0);
constant r_lut : t_palette := (
- x"00", x"00", x"00", x"00", x"AA", x"AA", x"AA", x"AA",
- x"55", x"55", x"55", x"55", x"FF", x"FF", x"FF", x"FF"
- );
+ x"00", x"00", x"00", x"00", x"AA", x"AA", x"AA", x"AA",
+ x"55", x"55", x"55", x"55", x"FF", x"FF", x"FF", x"FF"
+ );
constant g_lut : t_palette := (
- x"00", x"00", x"AA", x"AA", x"00", x"00", x"55", x"AA",
- x"55", x"55", x"FF", x"FF", x"55", x"55", x"FF", x"FF"
- );
+ x"00", x"00", x"AA", x"AA", x"00", x"00", x"55", x"AA",
+ x"55", x"55", x"FF", x"FF", x"55", x"55", x"FF", x"FF"
+ );
constant b_lut : t_palette := (
- x"00", x"AA", x"00", x"AA", x"00", x"AA", x"00", x"AA",
- x"55", x"FF", x"55", x"FF", x"55", x"FF", x"55", x"FF"
- );
+ x"00", x"AA", x"00", x"AA", x"00", x"AA", x"00", x"AA",
+ x"55", x"FF", x"55", x"FF", x"55", x"FF", x"55", x"FF"
+ );
- signal overlay_demux_p :integer;
- signal overlay_demux :integer;
- signal overlay_data : integer;
+ signal overlay_demux_p : integer;
+ signal overlay_demux : integer;
+ signal overlay_data : integer;
- signal fb_ps_clk : STD_LOGIC;
- signal fb_ps_en : STD_LOGIC;
- signal fb_ps_we : STD_LOGIC_VECTOR ( 3 downto 0 );
- signal fb_ps_addr : STD_LOGIC_VECTOR ( 19 downto 0 );
- signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 );
- signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal fb_ps_clk : std_logic;
+ signal fb_ps_en : std_logic;
+ signal fb_ps_we : std_logic_vector (3 downto 0);
+ signal fb_ps_addr : std_logic_vector (19 downto 0);
+ signal fb_ps_wrdata : std_logic_vector (31 downto 0);
+ signal fb_ps_rddata : std_logic_vector (31 downto 0);
- signal fb_pl_addr : STD_LOGIC_VECTOR ( 14 downto 0 );
- signal fb_pl_rddata : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal fb_pl_addr : std_logic_vector (14 downto 0);
+ signal fb_pl_rddata : std_logic_vector (31 downto 0);
begin
- fb_ram0: entity work.blk_mem_gen_1
- port map (
- clka => fb_ps_clk,
- ena => fb_ps_en,
- wea => fb_ps_we,
- addra => fb_ps_addr (15 downto 2),
- dina => fb_ps_wrdata,
- douta => fb_ps_rddata,
- clkb => overlay_clk,
- web => "0000",
- addrb => fb_pl_addr,
- dinb => x"00000000",
- doutb => fb_pl_rddata
- );
-
-
-
- fb_pl_addr <= overlay_addr(17 downto 3);
-
- process (overlay_clk) begin
- if rising_edge(overlay_clk) then
- overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4;
- overlay_demux <=overlay_demux_p;
- end if;
- end process;
-
- overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux)));
-
- overlay_gate <= '0' when overlay_data = 0 else '1';
- overlay_r <= r_lut(overlay_data);
- overlay_g <= g_lut(overlay_data);
- overlay_b <= b_lut(overlay_data);
-
-
- axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0
- port map (
- s_axi_aclk => s_axi_aclk,
- s_axi_aresetn => s_axi_aresetn,
-
- s_axi_awid => s_axi_awid ,
- s_axi_awaddr => s_axi_awaddr(19 downto 0) ,
- s_axi_awlen => s_axi_awlen ,
- s_axi_awsize => s_axi_awsize ,
- s_axi_awburst => s_axi_awburst ,
- s_axi_awlock => s_axi_awlock(0) ,
- s_axi_awcache => s_axi_awcache ,
- s_axi_awprot => s_axi_awprot ,
- s_axi_awvalid => s_axi_awvalid ,
- s_axi_awready => s_axi_awready ,
- s_axi_wdata => s_axi_wdata ,
- s_axi_wstrb => s_axi_wstrb ,
- s_axi_wlast => s_axi_wlast ,
- s_axi_wvalid => s_axi_wvalid ,
- s_axi_wready => s_axi_wready ,
- s_axi_bid => s_axi_bid ,
- s_axi_bresp => s_axi_bresp ,
- s_axi_bvalid => s_axi_bvalid ,
- s_axi_bready => s_axi_bready ,
- s_axi_arid => s_axi_arid ,
- s_axi_araddr => s_axi_araddr(19 downto 0) ,
- s_axi_arlen => s_axi_arlen ,
- s_axi_arsize => s_axi_arsize ,
- s_axi_arburst => s_axi_arburst ,
- s_axi_arlock => s_axi_arlock(0) ,
- s_axi_arcache => s_axi_arcache ,
- s_axi_arprot => s_axi_arprot ,
- s_axi_arvalid => s_axi_arvalid ,
- s_axi_arready => s_axi_arready ,
- s_axi_rid => s_axi_rid ,
- s_axi_rdata => s_axi_rdata ,
- s_axi_rresp => s_axi_rresp ,
- s_axi_rlast => s_axi_rlast ,
- s_axi_rvalid => s_axi_rvalid ,
- s_axi_rready => s_axi_rready ,
-
- bram_clk_a => fb_ps_clk ,
- bram_en_a => fb_ps_en ,
- bram_we_a => fb_ps_we ,
- bram_addr_a => fb_ps_addr ,
- bram_wrdata_a => fb_ps_wrdata ,
- bram_rddata_a => fb_ps_rddata
-
- );
+ fb_ram0 : entity work.blk_mem_gen_1
+ port map (
+ clka => fb_ps_clk,
+ ena => fb_ps_en,
+ wea => fb_ps_we,
+ addra => fb_ps_addr (15 downto 2),
+ dina => fb_ps_wrdata,
+ douta => fb_ps_rddata,
+ clkb => overlay_clk,
+ web => "0000",
+ addrb => fb_pl_addr,
+ dinb => x"00000000",
+ doutb => fb_pl_rddata
+ );
+
+
+
+ fb_pl_addr <= overlay_addr(17 downto 3);
+
+ process (overlay_clk)
+ begin
+ if rising_edge(overlay_clk) then
+ overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4;
+ overlay_demux <= overlay_demux_p;
+ end if;
+ end process;
+
+ overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux)));
+
+ overlay_gate <= '0' when overlay_data = 0 else '1';
+ overlay_r <= r_lut(overlay_data);
+ overlay_g <= g_lut(overlay_data);
+ overlay_b <= b_lut(overlay_data);
+
+
+ axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0
+ port map (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+
+ s_axi_awid => s_axi_awid,
+ s_axi_awaddr => s_axi_awaddr(19 downto 0),
+ s_axi_awlen => s_axi_awlen,
+ s_axi_awsize => s_axi_awsize,
+ s_axi_awburst => s_axi_awburst,
+ s_axi_awlock => s_axi_awlock(0),
+ s_axi_awcache => s_axi_awcache,
+ s_axi_awprot => s_axi_awprot,
+ s_axi_awvalid => s_axi_awvalid,
+ s_axi_awready => s_axi_awready,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_wstrb => s_axi_wstrb,
+ s_axi_wlast => s_axi_wlast,
+ s_axi_wvalid => s_axi_wvalid,
+ s_axi_wready => s_axi_wready,
+ s_axi_bid => s_axi_bid,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_bvalid => s_axi_bvalid,
+ s_axi_bready => s_axi_bready,
+ s_axi_arid => s_axi_arid,
+ s_axi_araddr => s_axi_araddr(19 downto 0),
+ s_axi_arlen => s_axi_arlen,
+ s_axi_arsize => s_axi_arsize,
+ s_axi_arburst => s_axi_arburst,
+ s_axi_arlock => s_axi_arlock(0),
+ s_axi_arcache => s_axi_arcache,
+ s_axi_arprot => s_axi_arprot,
+ s_axi_arvalid => s_axi_arvalid,
+ s_axi_arready => s_axi_arready,
+ s_axi_rid => s_axi_rid,
+ s_axi_rdata => s_axi_rdata,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rlast => s_axi_rlast,
+ s_axi_rvalid => s_axi_rvalid,
+ s_axi_rready => s_axi_rready,
+
+ bram_clk_a => fb_ps_clk,
+ bram_en_a => fb_ps_en,
+ bram_we_a => fb_ps_we,
+ bram_addr_a => fb_ps_addr,
+ bram_wrdata_a => fb_ps_wrdata,
+ bram_rddata_a => fb_ps_rddata
+
+ );
end Behavioural;
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index 5c29ff6..a78238e 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -75,12 +75,12 @@ begin
video_out_index => open,
video_out_data => open,
video_out_valid => open,
- video_in_clk => open,
- video_in_addr => open,
- video_in_gate => '0',
- video_in_r => open,
- video_in_g => open,
- video_in_b => open
+ video_in_clk => open,
+ video_in_addr => open,
+ video_in_gate => '0',
+ video_in_r => open,
+ video_in_g => open,
+ video_in_b => open
);
end Behavioral;
diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl
index 57c0f8b..25ad81e 100644
--- a/fpga/hp_lcd_driver/kbd_uarts.vhdl
+++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl
@@ -5,215 +5,250 @@ use work.all;
entity kbd_uarts is
port (
- s_axi_aclk : in STD_LOGIC;
- s_axi_aresetn : in STD_LOGIC;
- s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_awlock : in STD_LOGIC_VECTOR(1 downto 0);
- s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_awvalid : in STD_LOGIC;
- s_axi_awready : out STD_LOGIC;
- s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_wlast : in STD_LOGIC;
- s_axi_wvalid : in STD_LOGIC;
- s_axi_wready : out STD_LOGIC;
- s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_bvalid : out STD_LOGIC;
- s_axi_bready : in STD_LOGIC;
- s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_arlock : in STD_LOGIC_VECTOR( 1 downto 0);
- s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
- s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
- s_axi_arvalid : in STD_LOGIC;
- s_axi_arready : out STD_LOGIC;
- s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
- s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
- s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
- s_axi_rlast : out STD_LOGIC;
- s_axi_rvalid : out STD_LOGIC;
- s_axi_rready : in STD_LOGIC;
+ s_axi_aclk : in std_logic;
+ s_axi_aresetn : in std_logic;
- u0_tx: out std_logic;
- u0_rx: in std_logic;
- u0_int: out std_logic;
+ s_axi_arvalid : in STD_LOGIC;
+ s_axi_awvalid : in STD_LOGIC;
+ s_axi_bready : in STD_LOGIC;
+ s_axi_rready : in STD_LOGIC;
+ s_axi_wlast : in STD_LOGIC;
+ s_axi_wvalid : in STD_LOGIC;
+ s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
+ s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
+ s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
+ s_axi_arready : out STD_LOGIC;
+ s_axi_awready : out STD_LOGIC;
+ s_axi_bvalid : out STD_LOGIC;
+ s_axi_rlast : out STD_LOGIC;
+ s_axi_rvalid : out STD_LOGIC;
+ s_axi_wready : out STD_LOGIC;
+ s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
+ s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
+ s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
+
+ u0_tx : out std_logic;
+ u0_rx : in std_logic;
+ u0_int : out std_logic;
- u1_tx: out std_logic;
- u1_rx: in std_logic;
- u1_int: out std_logic
-);
+ u1_tx : out std_logic;
+ u1_rx : in std_logic;
+ u1_int : out std_logic
+ );
end kbd_uarts;
architecture Behavioural of kbd_uarts is
- signal uc_axi_awid : std_logic_vector ( 23 downto 0 );
- signal uc_axi_awaddr : std_logic_vector ( 63 downto 0 );
- signal uc_axi_awlen : std_logic_vector ( 15 downto 0 );
- signal uc_axi_awsize : std_logic_vector ( 5 downto 0 );
- signal uc_axi_awburst : std_logic_vector ( 3 downto 0 );
- signal uc_axi_awlock : std_logic_vector ( 1 downto 0 );
- signal uc_axi_awcache : std_logic_vector ( 7 downto 0 );
- signal uc_axi_awprot : std_logic_vector ( 5 downto 0 );
- signal uc_axi_awregion : std_logic_vector ( 7 downto 0 );
- signal uc_axi_awqos : std_logic_vector ( 7 downto 0 );
- signal uc_axi_awvalid : std_logic_vector ( 1 downto 0 );
- signal uc_axi_awready : std_logic_vector ( 1 downto 0 );
- signal uc_axi_wdata : std_logic_vector ( 63 downto 0 );
- signal uc_axi_wstrb : std_logic_vector ( 7 downto 0 );
- signal uc_axi_wlast : std_logic_vector ( 1 downto 0 );
- signal uc_axi_wvalid : std_logic_vector ( 1 downto 0 );
- signal uc_axi_wready : std_logic_vector ( 1 downto 0 );
- signal uc_axi_bid : std_logic_vector ( 23 downto 0 );
- signal uc_axi_bresp : std_logic_vector ( 3 downto 0 );
- signal uc_axi_bvalid : std_logic_vector ( 1 downto 0 );
- signal uc_axi_bready : std_logic_vector ( 1 downto 0 );
- signal uc_axi_arid : std_logic_vector ( 23 downto 0 );
- signal uc_axi_araddr : std_logic_vector ( 63 downto 0 );
- signal uc_axi_arlen : std_logic_vector ( 15 downto 0 );
- signal uc_axi_arsize : std_logic_vector ( 5 downto 0 );
- signal uc_axi_arburst : std_logic_vector ( 3 downto 0 );
- signal uc_axi_arlock : std_logic_vector ( 1 downto 0 );
- signal uc_axi_arcache : std_logic_vector ( 7 downto 0 );
- signal uc_axi_arprot : std_logic_vector ( 5 downto 0 );
- signal uc_axi_arregion : std_logic_vector ( 7 downto 0 );
- signal uc_axi_arqos : std_logic_vector ( 7 downto 0 );
- signal uc_axi_arvalid : std_logic_vector ( 1 downto 0 );
- signal uc_axi_arready : std_logic_vector ( 1 downto 0 );
- signal uc_axi_rid : std_logic_vector ( 23 downto 0 );
- signal uc_axi_rdata : std_logic_vector ( 63 downto 0 );
- signal uc_axi_rresp : std_logic_vector ( 3 downto 0 );
- signal uc_axi_rlast : std_logic_vector ( 1 downto 0 );
- signal uc_axi_rvalid : std_logic_vector ( 1 downto 0 );
- signal uc_axi_rready : std_logic_vector ( 1 downto 0 );
+
+ signal m_axi_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m_axi_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal m_axi_awvalid : STD_LOGIC;
+ signal m_axi_awready : STD_LOGIC;
+ signal m_axi_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m_axi_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal m_axi_wvalid : STD_LOGIC;
+ signal m_axi_wready : STD_LOGIC;
+ signal m_axi_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m_axi_bvalid : STD_LOGIC;
+ signal m_axi_bready : STD_LOGIC;
+ signal m_axi_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m_axi_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
+ signal m_axi_arvalid : STD_LOGIC;
+ signal m_axi_arready : STD_LOGIC;
+ signal m_axi_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
+ signal m_axi_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal m_axi_rvalid : STD_LOGIC;
+ signal m_axi_rready : STD_LOGIC;
+
+
+ signal uc_axi_awaddr : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal uc_axi_awprot : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal uc_axi_awvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_awready : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_wdata : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal uc_axi_wstrb : STD_LOGIC_VECTOR ( 7 downto 0 );
+ signal uc_axi_wvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_wready : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_bresp : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal uc_axi_bvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_bready : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_araddr : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal uc_axi_arprot : STD_LOGIC_VECTOR ( 5 downto 0 );
+ signal uc_axi_arvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_arready : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_rdata : STD_LOGIC_VECTOR ( 63 downto 0 );
+ signal uc_axi_rresp : STD_LOGIC_VECTOR ( 3 downto 0 );
+ signal uc_axi_rvalid : STD_LOGIC_VECTOR ( 1 downto 0 );
+ signal uc_axi_rready : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
-axi_crossbar_0_i: entity work.axi_crossbar_0
+
+
+axi_protocol_converter_0_i: entity work.axi_protocol_converter_0
Port map (
- aclk => s_axi_aclk,
- aresetn => s_axi_aresetn,
- s_axi_awid => s_axi_awid,
- s_axi_awaddr => s_axi_awaddr,
- s_axi_awlen => s_axi_awlen,
- s_axi_awsize => s_axi_awsize,
- s_axi_awburst => s_axi_awburst,
- s_axi_awlock => s_axi_awlock,
- s_axi_awcache => s_axi_awcache,
- s_axi_awprot => s_axi_awprot,
- s_axi_awqos => s_axi_awqos,
+ aclk => s_axi_aclk,
+ aresetn => s_axi_aresetn,
+
+ s_axi_arvalid => s_axi_arvalid,
s_axi_awvalid => s_axi_awvalid,
- s_axi_awready => s_axi_awready,
- s_axi_wdata => s_axi_wdata,
- s_axi_wstrb => s_axi_wstrb,
+ s_axi_bready => s_axi_bready,
+ s_axi_rready => s_axi_rready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
- s_axi_wready => s_axi_wready,
- s_axi_bid => s_axi_bid,
- s_axi_bresp => s_axi_bresp,
- s_axi_bvalid => s_axi_bvalid,
- s_axi_bready => s_axi_bready,
s_axi_arid => s_axi_arid,
- s_axi_araddr => s_axi_araddr,
- s_axi_arlen => s_axi_arlen,
- s_axi_arsize => s_axi_arsize,
+ s_axi_awid => s_axi_awid,
s_axi_arburst => s_axi_arburst,
s_axi_arlock => s_axi_arlock,
- s_axi_arcache => s_axi_arcache,
+ s_axi_arsize => s_axi_arsize,
+ s_axi_awburst => s_axi_awburst,
+ s_axi_awlock => s_axi_awlock,
+ s_axi_awsize => s_axi_awsize,
s_axi_arprot => s_axi_arprot,
+ s_axi_awprot => s_axi_awprot,
+ s_axi_araddr => s_axi_araddr,
+ s_axi_awaddr => s_axi_awaddr,
+ s_axi_wdata => s_axi_wdata,
+ s_axi_arcache => s_axi_arcache,
+ s_axi_arlen => s_axi_arlen,
s_axi_arqos => s_axi_arqos,
- s_axi_arvalid => s_axi_arvalid,
+ s_axi_awcache => s_axi_awcache,
+ s_axi_awlen => s_axi_awlen,
+ s_axi_awqos => s_axi_awqos,
+ s_axi_wstrb => s_axi_wstrb,
s_axi_arready => s_axi_arready,
- s_axi_rid => s_axi_rid,
- s_axi_rdata => s_axi_rdata,
- s_axi_rresp => s_axi_rresp,
+ s_axi_awready => s_axi_awready,
+ s_axi_bvalid => s_axi_bvalid,
s_axi_rlast => s_axi_rlast,
s_axi_rvalid => s_axi_rvalid,
- s_axi_rready => s_axi_rready,
+ s_axi_wready => s_axi_wready,
+ s_axi_bid => s_axi_bid,
+ s_axi_rid => s_axi_rid,
+ s_axi_bresp => s_axi_bresp,
+ s_axi_rresp => s_axi_rresp,
+ s_axi_rdata => s_axi_rdata,
- m_axi_awid => uc_axi_awid,
- m_axi_awaddr => uc_axi_awaddr,
- m_axi_awlen => uc_axi_awlen,
- m_axi_awsize => uc_axi_awsize,
- m_axi_awburst => uc_axi_awburst,
- m_axi_awlock => uc_axi_awlock,
- m_axi_awcache => uc_axi_awcache,
- m_axi_awprot => uc_axi_awprot,
- m_axi_awregion => uc_axi_awregion,
- m_axi_awqos => uc_axi_awqos,
- m_axi_awvalid => uc_axi_awvalid,
- m_axi_awready => uc_axi_awready,
- m_axi_wdata => uc_axi_wdata,
- m_axi_wstrb => uc_axi_wstrb,
- m_axi_wlast => uc_axi_wlast,
- m_axi_wvalid => uc_axi_wvalid,
- m_axi_wready => uc_axi_wready,
- m_axi_bid => uc_axi_bid,
- m_axi_bresp => uc_axi_bresp,
- m_axi_bvalid => uc_axi_bvalid,
- m_axi_bready => uc_axi_bready,
- m_axi_arid => uc_axi_arid,
--- m_axi_araddr => uc_axi_araddr,
- m_axi_arlen => uc_axi_arlen,
- m_axi_arsize => uc_axi_arsize,
- m_axi_arburst => uc_axi_arburst,
- m_axi_arlock => uc_axi_arlock,
- m_axi_arcache => uc_axi_arcache,
- m_axi_arprot => uc_axi_arprot,
- m_axi_arregion => uc_axi_arregion,
- m_axi_arqos => uc_axi_arqos,
- m_axi_arvalid => uc_axi_arvalid,
- m_axi_arready => uc_axi_arready,
- m_axi_rid => uc_axi_rid,
- m_axi_rdata => uc_axi_rdata,
- m_axi_rresp => uc_axi_rresp,
- m_axi_rlast => uc_axi_rlast,
- m_axi_rvalid => uc_axi_rvalid,
- m_axi_rready => uc_axi_rready
- );
-uc_axi_araddr <= ( others => '0');
+ m_axi_awaddr => m_axi_awaddr,
+ m_axi_awprot => m_axi_awprot,
+ m_axi_awvalid => m_axi_awvalid,
+ m_axi_awready => m_axi_awready,
+ m_axi_wdata => m_axi_wdata,
+ m_axi_wstrb => m_axi_wstrb,
+ m_axi_wvalid => m_axi_wvalid,
+ m_axi_wready => m_axi_wready,
+ m_axi_bresp => m_axi_bresp,
+ m_axi_bvalid => m_axi_bvalid,
+ m_axi_bready => m_axi_bready,
+ m_axi_araddr => m_axi_araddr,
+ m_axi_arprot => m_axi_arprot,
+ m_axi_arvalid => m_axi_arvalid,
+ m_axi_arready => m_axi_arready,
+ m_axi_rdata => m_axi_rdata,
+ m_axi_rresp => m_axi_rresp,
+ m_axi_rvalid => m_axi_rvalid,
+ m_axi_rready => m_axi_rready
+ );
-axi_uart16550_0_i0: entity work.axi_uart16550_0
-port map (
- s_axi_aclk => s_axi_aclk,
- s_axi_aresetn => s_axi_aresetn,
+ axi_crossbar_0_i : entity work.axi_crossbar_0
+ port map (
+ aclk => s_axi_aclk,
+ aresetn => s_axi_aresetn,
+ s_axi_awaddr => m_axi_awaddr ,
+ s_axi_awprot => m_axi_awprot ,
+ s_axi_awvalid => m_axi_awvalid ,
+ s_axi_awready => m_axi_awready ,
+ s_axi_wdata => m_axi_wdata ,
+ s_axi_wstrb => m_axi_wstrb ,
+ s_axi_wvalid => m_axi_wvalid ,
+ s_axi_wready => m_axi_wready ,
+ s_axi_bresp => m_axi_bresp ,
+ s_axi_bvalid => m_axi_bvalid ,
+ s_axi_bready => m_axi_bready ,
+ s_axi_araddr => m_axi_araddr ,
+ s_axi_arprot => m_axi_arprot ,
+ s_axi_arvalid => m_axi_arvalid ,
+ s_axi_arready => m_axi_arready ,
+ s_axi_rdata => m_axi_rdata ,
+ s_axi_rresp => m_axi_rresp ,
+ s_axi_rvalid => m_axi_rvalid ,
+ s_axi_rready => m_axi_rready ,
+ m_axi_awaddr => uc_axi_awaddr ,
+ m_axi_awprot => uc_axi_awprot ,
+ m_axi_awvalid => uc_axi_awvalid ,
+ m_axi_awready => uc_axi_awready ,
+ m_axi_wdata => uc_axi_wdata ,
+ m_axi_wstrb => uc_axi_wstrb ,
+ m_axi_wvalid => uc_axi_wvalid ,
+ m_axi_wready => uc_axi_wready ,
+ m_axi_bresp => uc_axi_bresp ,
+ m_axi_bvalid => uc_axi_bvalid ,
+ m_axi_bready => uc_axi_bready ,
+ m_axi_araddr => uc_axi_araddr ,
+ m_axi_arprot => uc_axi_arprot ,
+ m_axi_arvalid => uc_axi_arvalid ,
+ m_axi_arready => uc_axi_arready ,
+ m_axi_rdata => uc_axi_rdata ,
+ m_axi_rresp => uc_axi_rresp ,
+ m_axi_rvalid => uc_axi_rvalid ,
+ m_axi_rready => uc_axi_rready
+);
- s_axi_awaddr => uc_axi_awaddr(12 downto 0),
- s_axi_awvalid => uc_axi_awvalid(0),
- s_axi_awready => uc_axi_awready(0),
- s_axi_wdata => uc_axi_wdata(31 downto 0),
- s_axi_wstrb => uc_axi_wstrb (3 downto 0),
- s_axi_wvalid => uc_axi_wvalid(0),
- s_axi_wready => uc_axi_wready(0),
- s_axi_bresp => uc_axi_bresp(1 downto 0),
- s_axi_bvalid =>uc_axi_bvalid(0),
- s_axi_bready =>uc_axi_bready(0),
- s_axi_araddr => uc_axi_araddr(12 downto 0),
- s_axi_arvalid => uc_axi_arvalid(0),
- s_axi_arready => uc_axi_arready(0),
- s_axi_rdata => uc_axi_rdata(31 downto 0),
- s_axi_rresp => uc_axi_rresp(1 downto 0),
- s_axi_rvalid => uc_axi_rvalid(0),
- s_axi_rready => uc_axi_rready(0),
- ip2intc_irpt => u0_int,
- freeze => '0',
+ axi_uart16550_0_i0 : entity work.axi_uart16550_0
+ port map (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
- sin => u0_rx,
- sout => u0_tx
+ s_axi_awaddr => uc_axi_awaddr(12 downto 0),
+ s_axi_awvalid => uc_axi_awvalid(0),
+ s_axi_awready => uc_axi_awready(0),
+ s_axi_wdata => uc_axi_wdata(31 downto 0),
+ s_axi_wstrb => uc_axi_wstrb (3 downto 0),
+ s_axi_wvalid => uc_axi_wvalid(0),
+ s_axi_wready => uc_axi_wready(0),
+ s_axi_bresp => uc_axi_bresp(1 downto 0),
+ s_axi_bvalid => uc_axi_bvalid(0),
+ s_axi_bready => uc_axi_bready(0),
+ s_axi_araddr => uc_axi_araddr(12 downto 0),
+ s_axi_arvalid => uc_axi_arvalid(0),
+ s_axi_arready => uc_axi_arready(0),
+ s_axi_rdata => uc_axi_rdata(31 downto 0),
+ s_axi_rresp => uc_axi_rresp(1 downto 0),
+ s_axi_rvalid => uc_axi_rvalid(0),
+ s_axi_rready => uc_axi_rready(0),
+ ip2intc_irpt => u0_int,
+ freeze => '0',
+ sin => u1_tx,
+ sout => u0_tx,
+ ctsn => '0',
+ dcdn =>'0',
+ dsrn => '0',
+ rin => '1'
+
-- baudoutn : out STD_LOGIC;
-- ctsn : in STD_LOGIC;
-- dcdn : in STD_LOGIC;
@@ -226,40 +261,40 @@ port map (
-- rtsn : out STD_LOGIC;
-- rxrdyn : out STD_LOGIC;
-- txrdyn : out STD_LOGIC;
-);
-
-axi_uart16550_0_i1: entity work.axi_uart16550_0
-port map (
- s_axi_aclk => s_axi_aclk,
- s_axi_aresetn => s_axi_aresetn,
-
-
+ );
- s_axi_awaddr => uc_axi_awaddr(44 downto 32),
- s_axi_awvalid => uc_axi_awvalid(1),
- s_axi_awready => uc_axi_awready(1),
- s_axi_wdata => uc_axi_wdata(63 downto 32),
- s_axi_wstrb => uc_axi_wstrb (7 downto 4),
- s_axi_wvalid => uc_axi_wvalid(1),
- s_axi_wready => uc_axi_wready(1),
- s_axi_bresp => uc_axi_bresp(3 downto 2),
- s_axi_bvalid =>uc_axi_bvalid(1),
- s_axi_bready =>uc_axi_bready(1),
- s_axi_araddr => uc_axi_araddr(44 downto 32),
- s_axi_arvalid => uc_axi_arvalid(1),
- s_axi_arready => uc_axi_arready(1),
- s_axi_rdata => uc_axi_rdata(63 downto 32),
- s_axi_rresp => uc_axi_rresp(3 downto 2),
- s_axi_rvalid => uc_axi_rvalid(1),
- s_axi_rready => uc_axi_rready(1),
+ axi_uart16550_0_i1 : entity work.axi_uart16550_0
+ port map (
+ s_axi_aclk => s_axi_aclk,
+ s_axi_aresetn => s_axi_aresetn,
+ s_axi_awaddr => uc_axi_awaddr(44 downto 32),
+ s_axi_awvalid => uc_axi_awvalid(1),
+ s_axi_awready => uc_axi_awready(1),
+ s_axi_wdata => uc_axi_wdata(63 downto 32),
+ s_axi_wstrb => uc_axi_wstrb (7 downto 4),
+ s_axi_wvalid => uc_axi_wvalid(1),
+ s_axi_wready => uc_axi_wready(1),
+ s_axi_bresp => uc_axi_bresp(3 downto 2),
+ s_axi_bvalid => uc_axi_bvalid(1),
+ s_axi_bready => uc_axi_bready(1),
+ s_axi_araddr => uc_axi_araddr(44 downto 32),
+ s_axi_arvalid => uc_axi_arvalid(1),
+ s_axi_arready => uc_axi_arready(1),
+ s_axi_rdata => uc_axi_rdata(63 downto 32),
+ s_axi_rresp => uc_axi_rresp(3 downto 2),
+ s_axi_rvalid => uc_axi_rvalid(1),
+ s_axi_rready => uc_axi_rready(1),
- ip2intc_irpt => u1_int,
- freeze => '0',
-
- sin => u1_rx,
- sout => u1_tx
-
+ ip2intc_irpt => u1_int,
+ freeze => '0',
+ sin => u0_tx,
+ sout => u1_tx,
+ ctsn => '0',
+ dcdn =>'0',
+ dsrn => '0',
+ rin => '1'
+
-- baudoutn : out STD_LOGIC;
-- ctsn : in STD_LOGIC;
-- dcdn : in STD_LOGIC;
@@ -272,7 +307,6 @@ port map (
-- rtsn : out STD_LOGIC;
-- rxrdyn : out STD_LOGIC;
-- txrdyn : out STD_LOGIC;
-);
-
+ );
end Behavioural;
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index 4787dc6..6ae694b 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -137,7 +137,7 @@ begin
o => grid_d
);
- r <= r_in; -- when grid_d='0' else x"ff";
+ r <= r_in; -- when grid_d='0' else x"ff";
g <= g_in;
b <= b_in;
diff --git a/fpga/hp_lcd_driver/tmds_encode.vhdl b/fpga/hp_lcd_driver/tmds_encode.vhdl
index ed5e288..cfd2368 100644
--- a/fpga/hp_lcd_driver/tmds_encode.vhdl
+++ b/fpga/hp_lcd_driver/tmds_encode.vhdl
@@ -31,7 +31,7 @@ architecture beh of tmds_encode is
begin
-- c_p10 <= "1111000001";
- c_p10 <= "1111100000";
+ c_p10 <= "1111100000";
-- c_p10 <= "0111110000";
-- c_p10 <= "0011111000";
-- c_p10 <= "0001111100";
diff --git a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
index 8749d3f..f804024 100644
--- a/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_output_artix7.vhdl
@@ -35,7 +35,7 @@ end tmds_output;
architecture beh of tmds_output is
signal phy_reset : std_logic;
- signal b : natural range 0 to 9:= 0;
+ signal b : natural range 0 to 9 := 0;
begin
diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
index 81e4b7e..4d00c91 100644
--- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
+++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl
@@ -21,9 +21,9 @@ end tmds_phy_artix7;
architecture beh of tmds_phy_artix7 is
- signal ld : std_logic_vector(9 downto 0);
+ signal ld : std_logic_vector(9 downto 0);
signal ld2 : std_logic_vector(9 downto 0);
- signal sr : std_logic_vector(9 downto 0);
+ signal sr : std_logic_vector(9 downto 0);
signal s : std_logic;
@@ -70,15 +70,15 @@ begin
process(phy_clk)
begin
if rising_edge(phy_clk) then
- if b=5 then
- ld<=ld2;
- end if;
+ if b = 5 then
+ ld <= ld2;
+ end if;
if b = 0 then
sr <= ld;
else
sr(8 downto 0) <= sr (9 downto 1);
end if;
- s <= sr(0);
+ s <= sr(0);
end if;
end process;
diff --git a/fpga/hp_lcd_driver/vnc_hw.vhdl b/fpga/hp_lcd_driver/vnc_hw.vhdl
index a4ea94a..42ee1f2 100644
--- a/fpga/hp_lcd_driver/vnc_hw.vhdl
+++ b/fpga/hp_lcd_driver/vnc_hw.vhdl
@@ -8,10 +8,10 @@ entity vnc_hw is
video_width : integer := 2
);
port (
- vnc_clk : in std_logic;
- vnc_valid : in std_logic;
- vnc_data : in std_logic_vector(video_width -1 downto 0);
- vnc_index : in std_logic;
+ vnc_clk : in std_logic;
+ vnc_valid : in std_logic;
+ vnc_data : in std_logic_vector(video_width -1 downto 0);
+ vnc_index : in std_logic;
sys_rst_n : in std_logic;
@@ -31,7 +31,7 @@ entity vnc_hw is
axi_wready : in std_logic;
axi_bvalid : in std_logic;
axi_bready : out std_logic
-);
+ );
end vnc_hw;
architecture Behavioural of vnc_hw is
diff --git a/fpga/hp_lcd_driver/vnc_serializer.vhdl b/fpga/hp_lcd_driver/vnc_serializer.vhdl
index 9ec89a8..1662db8 100644
--- a/fpga/hp_lcd_driver/vnc_serializer.vhdl
+++ b/fpga/hp_lcd_driver/vnc_serializer.vhdl
@@ -26,17 +26,17 @@ architecture Behavioural of vnc_serializer is
signal wren : std_logic;
signal next_index : std_logic;
signal index : std_logic;
- signal rgb : std_logic_vector(7 downto 0);
+ signal rgb : std_logic_vector(7 downto 0);
begin
- rgb(2 downto 0) <= "111" when vnc_data(0)='1' else
- "000";
- rgb(5 downto 3) <= "111" when vnc_data(1)='1' and vnc_data(3)='1' else
- "100" when vnc_data(1)='1' else
- "000";
- rgb(7 downto 6) <= "11" when vnc_data(2)='1' and vnc_data(3)='1' else
- "10" when vnc_data(2)='1' else
- "00";
+ rgb(2 downto 0) <= "111" when vnc_data(0) = '1' else
+ "000";
+ rgb(5 downto 3) <= "111" when vnc_data(1) = '1' and vnc_data(3) = '1' else
+ "100" when vnc_data(1) = '1' else
+ "000";
+ rgb(7 downto 6) <= "11" when vnc_data(2) = '1' and vnc_data(3) = '1' else
+ "10" when vnc_data(2) = '1' else
+ "00";
process (clk)
@@ -44,12 +44,12 @@ begin
if rising_edge(clk) then
if vnc_valid = '1' then
if vnc_index = '1' then
- reg(0)<=rgb;
+ reg(0) <= rgb;
next_index <= '1';
i <= 1;
wren <= '0';
else
- reg(i) <=rgb;
+ reg(i) <= rgb;
if i /= 7 then
i <= i+1;
wren <= '0';
@@ -71,7 +71,7 @@ begin
g_j : for j in 0 to 7 generate
-- fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j);
-- fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0');
- fifo_data(((j*8)+7) downto (j*8)) <= reg(j);
+ fifo_data(((j*8)+7) downto (j*8)) <= reg(j);
end generate g_j;
fifo_data(64) <= index;
diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl
index 6fdc3b1..82186e1 100644
--- a/fpga/hp_lcd_driver/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver/vram_artix7.vhdl
@@ -18,7 +18,7 @@ entity vram is
end vram;
architecture beh of vram is
- signal wr_en_v : std_logic_vector(0 downto 0);
+ signal wr_en_v : std_logic_vector(0 downto 0);
begin
wr_en_v(0) <= wr_en;
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
index 31afd86..cbe9443 100644
--- a/fpga/hp_lcd_driver/zynq7.mk
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -9,6 +9,7 @@ IP= \
zynq7_ip/processing_system7_0.tcl \
zynq7_ip/fifo_generator_0.tcl \
zynq7_ip/axi_uart16550_0.tcl \
+ zynq7_ip/axi_protocol_converter_0.tcl \
zynq7_ip/axi_crossbar_0.tcl
diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
index a73d793..babb0a7 100644
--- a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
@@ -39,6 +39,7 @@ read_ip $ip_dir/axi_bram_ctrl_0/axi_bram_ctrl_0.xci
read_ip $ip_dir/processing_system7_0/processing_system7_0.xci
read_ip $ip_dir/fifo_generator_0/fifo_generator_0.xci
read_ip $ip_dir/axi_uart16550_0/axi_uart16550_0.xci
+read_ip $ip_dir/axi_protocol_converter_0/axi_protocol_converter_0.xci
read_ip $ip_dir/axi_crossbar_0/axi_crossbar_0.xci
read_xdc $normal_xdc
diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl
index 74025a8..b24f354 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl
@@ -6,15 +6,47 @@ source $source_dir/zynq7_config.tcl
create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name axi_crossbar_0 -dir $ip_dir
set_property -dict [list \
- CONFIG.NUM_SI {1} \
+ CONFIG.ADDR_RANGES {1} \
+ CONFIG.ADDR_WIDTH {32} \
+ CONFIG.ARUSER_WIDTH {0} \
+ CONFIG.AWUSER_WIDTH {0} \
+ CONFIG.BUSER_WIDTH {0} \
+ CONFIG.CONNECTIVITY_MODE {SASD} \
+ CONFIG.Component_Name {axi_crossbar_1} \
+ CONFIG.DATA_WIDTH {32} \
+ CONFIG.ID_WIDTH {0} \
+ CONFIG.M00_A00_ADDR_WIDTH {12} \
+ CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \
+ CONFIG.M00_ERR_MODE {0} \
+ CONFIG.M00_READ_ISSUING {1} \
+ CONFIG.M00_S00_READ_CONNECTIVITY {1} \
+ CONFIG.M00_S00_WRITE_CONNECTIVITY {1} \
+ CONFIG.M00_SECURE {0} \
+ CONFIG.M00_WRITE_ISSUING {1} \
+ CONFIG.M01_A00_ADDR_WIDTH {12} \
+ CONFIG.M01_A00_BASE_ADDR {0x0000000000001000} \
+ CONFIG.M01_ERR_MODE {0} \
+ CONFIG.M01_READ_ISSUING {1} \
+ CONFIG.M01_S00_READ_CONNECTIVITY {1} \
+ CONFIG.M01_S00_WRITE_CONNECTIVITY {1} \
+ CONFIG.M01_SECURE {0} \
+ CONFIG.M01_WRITE_ISSUING {1} \
CONFIG.NUM_MI {2} \
- CONFIG.ID_WIDTH {12} \
- CONFIG.S00_THREAD_ID_WIDTH {12} \
- CONFIG.S00_BASE_ID {0x80000000} \
- CONFIG.M00_A00_BASE_ADDR {0x80000000} \
- CONFIG.M01_A00_BASE_ADDR {0x80001000} \
+ CONFIG.NUM_SI {1} \
+ CONFIG.PROTOCOL {AXI4LITE} \
+ CONFIG.RUSER_WIDTH {0} \
+ CONFIG.R_REGISTER {1} \
+ CONFIG.S00_ARB_PRIORITY {0} \
+ CONFIG.S00_BASE_ID {0x00000000} \
+ CONFIG.S00_READ_ACCEPTANCE {1} \
+ CONFIG.S00_SINGLE_THREAD {1} \
+ CONFIG.S00_THREAD_ID_WIDTH {0} \
+ CONFIG.S00_WRITE_ACCEPTANCE {1} \
+ CONFIG.STRATEGY {0} \
+ CONFIG.WUSER_WIDTH {0} \
] [get_ips axi_crossbar_0]
+
generate_target all [get_ips]
synth_ip [get_ips]
diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_protocol_converter_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_protocol_converter_0.tcl
new file mode 100644
index 0000000..a7adec2
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_ip/axi_protocol_converter_0.tcl
@@ -0,0 +1,25 @@
+set source_dir [file dirname [file dirname [file normalize [info script]]]]
+
+source $source_dir/zynq7_config.tcl
+
+create_ip -name axi_protocol_converter -vendor xilinx.com -library ip -version 2.1 -module_name axi_protocol_converter_0 -dir $ip_dir
+
+set_property -dict [ list \
+ CONFIG.ADDR_WIDTH {32} \
+ CONFIG.ARUSER_WIDTH {0} \
+ CONFIG.AWUSER_WIDTH {0} \
+ CONFIG.BUSER_WIDTH {0} \
+ CONFIG.DATA_WIDTH {32} \
+ CONFIG.ID_WIDTH {12} \
+ CONFIG.MI_PROTOCOL {AXI4LITE} \
+ CONFIG.READ_WRITE_MODE {READ_WRITE} \
+ CONFIG.RUSER_WIDTH {0} \
+ CONFIG.SI_PROTOCOL {AXI4} \
+ CONFIG.TRANSLATION_MODE {2} \
+ CONFIG.WUSER_WIDTH {0} \
+ ] [get_ips axi_protocol_converter_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips]
+
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 1639572..5d0d3e5 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -91,12 +91,12 @@ entity zynq7_wrapper is
hdmi_b_n : out std_logic;
hdmi_vcc : out std_logic;
- u0_tx: out std_logic;
- u0_rx: in std_logic;
- u1_tx: out std_logic;
- u1_rx: in std_logic;
+ u0_tx : out std_logic;
+ u0_rx : in std_logic;
+ u1_tx : out std_logic;
+ u1_rx : in std_logic;
- scope_ch1: out std_logic
+ scope_ch1 : out std_logic
);
end entity zynq7_wrapper;
@@ -115,86 +115,86 @@ architecture arch of zynq7_wrapper is
signal gp01_aclk : std_logic;
signal gp01_nrst : std_logic;
- signal gp0_arvalid : std_logic;
- signal gp0_awvalid : std_logic;
+ signal gp0_arvalid : std_logic;
+ signal gp0_awvalid : std_logic;
signal gp0_bready : std_logic;
signal gp0_rready : std_logic;
- signal gp0_wlast : std_logic;
+ signal gp0_wlast : std_logic;
signal gp0_wvalid : std_logic;
- signal gp0_arid : std_logic_vector ( 11 downto 0 );
- signal gp0_awid : std_logic_vector ( 11 downto 0 );
- signal gp0_wid : std_logic_vector ( 11 downto 0 );
- signal gp0_arburst : std_logic_vector ( 1 downto 0 );
- signal gp0_arlock : std_logic_vector ( 1 downto 0 );
- signal gp0_arsize : std_logic_vector ( 2 downto 0 );
- signal gp0_awburst : std_logic_vector ( 1 downto 0 );
- signal gp0_awlock : std_logic_vector ( 1 downto 0 );
- signal gp0_awsize : std_logic_vector ( 2 downto 0 );
- signal gp0_arprot : std_logic_vector ( 2 downto 0 );
- signal gp0_awprot : std_logic_vector ( 2 downto 0 );
- signal gp0_araddr : std_logic_vector ( 31 downto 0 );
- signal gp0_awaddr : std_logic_vector ( 31 downto 0 );
- signal gp0_wdata : std_logic_vector ( 31 downto 0 );
- signal gp0_arcache : std_logic_vector ( 3 downto 0 );
- signal gp0_arlen : std_logic_vector ( 3 downto 0 );
- signal gp0_arqos : std_logic_vector ( 3 downto 0 );
- signal gp0_awcache : std_logic_vector ( 3 downto 0 );
- signal gp0_awlen : std_logic_vector ( 3 downto 0 );
- signal gp0_awqos : std_logic_vector ( 3 downto 0 );
- signal gp0_wstrb : std_logic_vector ( 3 downto 0 );
- signal gp0_arready : std_logic;
- signal gp0_awready : std_logic;
+ signal gp0_arid : std_logic_vector (11 downto 0);
+ signal gp0_awid : std_logic_vector (11 downto 0);
+ signal gp0_wid : std_logic_vector (11 downto 0);
+ signal gp0_arburst : std_logic_vector (1 downto 0);
+ signal gp0_arlock : std_logic_vector (1 downto 0);
+ signal gp0_arsize : std_logic_vector (2 downto 0);
+ signal gp0_awburst : std_logic_vector (1 downto 0);
+ signal gp0_awlock : std_logic_vector (1 downto 0);
+ signal gp0_awsize : std_logic_vector (2 downto 0);
+ signal gp0_arprot : std_logic_vector (2 downto 0);
+ signal gp0_awprot : std_logic_vector (2 downto 0);
+ signal gp0_araddr : std_logic_vector (31 downto 0);
+ signal gp0_awaddr : std_logic_vector (31 downto 0);
+ signal gp0_wdata : std_logic_vector (31 downto 0);
+ signal gp0_arcache : std_logic_vector (3 downto 0);
+ signal gp0_arlen : std_logic_vector (3 downto 0);
+ signal gp0_arqos : std_logic_vector (3 downto 0);
+ signal gp0_awcache : std_logic_vector (3 downto 0);
+ signal gp0_awlen : std_logic_vector (3 downto 0);
+ signal gp0_awqos : std_logic_vector (3 downto 0);
+ signal gp0_wstrb : std_logic_vector (3 downto 0);
+ signal gp0_arready : std_logic;
+ signal gp0_awready : std_logic;
signal gp0_bvalid : std_logic;
- signal gp0_rlast : std_logic;
+ signal gp0_rlast : std_logic;
signal gp0_rvalid : std_logic;
signal gp0_wready : std_logic;
- signal gp0_bid : std_logic_vector ( 11 downto 0 );
- signal gp0_rid : std_logic_vector ( 11 downto 0 );
- signal gp0_bresp : std_logic_vector ( 1 downto 0 );
- signal gp0_rresp : std_logic_vector ( 1 downto 0 );
- signal gp0_rdata : std_logic_vector ( 31 downto 0 );
+ signal gp0_bid : std_logic_vector (11 downto 0);
+ signal gp0_rid : std_logic_vector (11 downto 0);
+ signal gp0_bresp : std_logic_vector (1 downto 0);
+ signal gp0_rresp : std_logic_vector (1 downto 0);
+ signal gp0_rdata : std_logic_vector (31 downto 0);
-signal gp1_arvalid : std_logic;
- signal gp1_awvalid : std_logic;
+ signal gp1_arvalid : std_logic;
+ signal gp1_awvalid : std_logic;
signal gp1_bready : std_logic;
signal gp1_rready : std_logic;
- signal gp1_wlast : std_logic;
+ signal gp1_wlast : std_logic;
signal gp1_wvalid : std_logic;
- signal gp1_arid : std_logic_vector ( 11 downto 0 );
- signal gp1_awid : std_logic_vector ( 11 downto 0 );
- signal gp1_wid : std_logic_vector ( 11 downto 0 );
- signal gp1_arburst : std_logic_vector ( 1 downto 0 );
- signal gp1_arlock : std_logic_vector ( 1 downto 0 );
- signal gp1_arsize : std_logic_vector ( 2 downto 0 );
- signal gp1_awburst : std_logic_vector ( 1 downto 0 );
- signal gp1_awlock : std_logic_vector ( 1 downto 0 );
- signal gp1_awsize : std_logic_vector ( 2 downto 0 );
- signal gp1_arprot : std_logic_vector ( 2 downto 0 );
- signal gp1_awprot : std_logic_vector ( 2 downto 0 );
- signal gp1_araddr : std_logic_vector ( 31 downto 0 );
- signal gp1_awaddr : std_logic_vector ( 31 downto 0 );
- signal gp1_wdata : std_logic_vector ( 31 downto 0 );
- signal gp1_arcache : std_logic_vector ( 3 downto 0 );
- signal gp1_arlen : std_logic_vector ( 3 downto 0 );
- signal gp1_arqos : std_logic_vector ( 3 downto 0 );
- signal gp1_awcache : std_logic_vector ( 3 downto 0 );
- signal gp1_awlen : std_logic_vector ( 3 downto 0 );
- signal gp1_awqos : std_logic_vector ( 3 downto 0 );
- signal gp1_wstrb : std_logic_vector ( 3 downto 0 );
- signal gp1_arready : std_logic;
- signal gp1_awready : std_logic;
+ signal gp1_arid : std_logic_vector (11 downto 0);
+ signal gp1_awid : std_logic_vector (11 downto 0);
+ signal gp1_wid : std_logic_vector (11 downto 0);
+ signal gp1_arburst : std_logic_vector (1 downto 0);
+ signal gp1_arlock : std_logic_vector (1 downto 0);
+ signal gp1_arsize : std_logic_vector (2 downto 0);
+ signal gp1_awburst : std_logic_vector (1 downto 0);
+ signal gp1_awlock : std_logic_vector (1 downto 0);
+ signal gp1_awsize : std_logic_vector (2 downto 0);
+ signal gp1_arprot : std_logic_vector (2 downto 0);
+ signal gp1_awprot : std_logic_vector (2 downto 0);
+ signal gp1_araddr : std_logic_vector (31 downto 0);
+ signal gp1_awaddr : std_logic_vector (31 downto 0);
+ signal gp1_wdata : std_logic_vector (31 downto 0);
+ signal gp1_arcache : std_logic_vector (3 downto 0);
+ signal gp1_arlen : std_logic_vector (3 downto 0);
+ signal gp1_arqos : std_logic_vector (3 downto 0);
+ signal gp1_awcache : std_logic_vector (3 downto 0);
+ signal gp1_awlen : std_logic_vector (3 downto 0);
+ signal gp1_awqos : std_logic_vector (3 downto 0);
+ signal gp1_wstrb : std_logic_vector (3 downto 0);
+ signal gp1_arready : std_logic;
+ signal gp1_awready : std_logic;
signal gp1_bvalid : std_logic;
- signal gp1_rlast : std_logic;
+ signal gp1_rlast : std_logic;
signal gp1_rvalid : std_logic;
signal gp1_wready : std_logic;
- signal gp1_bid : std_logic_vector ( 11 downto 0 );
- signal gp1_rid : std_logic_vector ( 11 downto 0 );
- signal gp1_bresp : std_logic_vector ( 1 downto 0 );
- signal gp1_rresp : std_logic_vector ( 1 downto 0 );
- signal gp1_rdata : std_logic_vector ( 31 downto 0 );
+ signal gp1_bid : std_logic_vector (11 downto 0);
+ signal gp1_rid : std_logic_vector (11 downto 0);
+ signal gp1_bresp : std_logic_vector (1 downto 0);
+ signal gp1_rresp : std_logic_vector (1 downto 0);
+ signal gp1_rdata : std_logic_vector (31 downto 0);
+
-
signal hp0_aclk : std_logic;
signal hp0_nrst : std_logic;
signal hp0_arvalid : std_logic;
@@ -231,16 +231,16 @@ signal gp1_arvalid : std_logic;
signal overlay_clk : std_logic;
signal overlay_addr : std_logic_vector(addr_width-1 downto 0);
- signal overlay_gate : std_logic;
- signal overlay_r : std_logic_vector(7 downto 0);
- signal overlay_g : std_logic_vector(7 downto 0);
- signal overlay_b : std_logic_vector(7 downto 0);
+ signal overlay_gate : std_logic;
+ signal overlay_r : std_logic_vector(7 downto 0);
+ signal overlay_g : std_logic_vector(7 downto 0);
+ signal overlay_b : std_logic_vector(7 downto 0);
+
-
begin
- scope_ch1 <= gp0_awvalid; --clk_50m_ps;
+ scope_ch1 <= gp0_awvalid; --clk_50m_ps;
@@ -279,12 +279,12 @@ begin
video_out_valid => vnc_valid,
video_out_data => vnc_data,
video_out_index => vnc_index,
- video_in_clk => overlay_clk,
- video_in_addr => overlay_addr,
- video_in_gate => overlay_gate,
- video_in_r => overlay_r,
- video_in_g => overlay_g,
- video_in_b => overlay_b
+ video_in_clk => overlay_clk,
+ video_in_addr => overlay_addr,
+ video_in_gate => overlay_gate,
+ video_in_r => overlay_r,
+ video_in_g => overlay_g,
+ video_in_b => overlay_b
);
processing_system7_0_i : entity work.processing_system7_0
@@ -339,86 +339,86 @@ begin
GPIO_T => emio_t,
- M_AXI_GP0_ARVALID => gp0_arvalid ,
- M_AXI_GP0_AWVALID => gp0_awvalid ,
- M_AXI_GP0_BREADY => gp0_bready ,
- M_AXI_GP0_RREADY => gp0_rready ,
- M_AXI_GP0_WLAST => gp0_wlast ,
- M_AXI_GP0_WVALID => gp0_wvalid ,
- M_AXI_GP0_ARID => gp0_arid ,
- M_AXI_GP0_AWID => gp0_awid ,
- M_AXI_GP0_WID => gp0_wid ,
- M_AXI_GP0_ARBURST => gp0_arburst ,
- M_AXI_GP0_ARLOCK => gp0_arlock ,
- M_AXI_GP0_ARSIZE => gp0_arsize ,
- M_AXI_GP0_AWBURST => gp0_awburst ,
- M_AXI_GP0_AWLOCK => gp0_awlock ,
- M_AXI_GP0_AWSIZE => gp0_awsize ,
- M_AXI_GP0_ARPROT => gp0_arprot ,
- M_AXI_GP0_AWPROT => gp0_awprot ,
- M_AXI_GP0_ARADDR => gp0_araddr ,
- M_AXI_GP0_AWADDR => gp0_awaddr ,
- M_AXI_GP0_WDATA => gp0_wdata ,
- M_AXI_GP0_ARCACHE => gp0_arcache ,
- M_AXI_GP0_ARLEN => gp0_arlen ,
- M_AXI_GP0_ARQOS => gp0_arqos ,
- M_AXI_GP0_AWCACHE => gp0_awcache ,
- M_AXI_GP0_AWLEN => gp0_awlen ,
- M_AXI_GP0_AWQOS => gp0_awqos ,
- M_AXI_GP0_WSTRB => gp0_wstrb ,
- M_AXI_GP0_ACLK => gp01_aclk ,
- M_AXI_GP0_ARREADY => gp0_arready ,
- M_AXI_GP0_AWREADY => gp0_awready ,
- M_AXI_GP0_BVALID => gp0_bvalid ,
- M_AXI_GP0_RLAST => gp0_rlast ,
- M_AXI_GP0_RVALID => gp0_rvalid ,
- M_AXI_GP0_WREADY => gp0_wready ,
- M_AXI_GP0_BID => gp0_bid ,
- M_AXI_GP0_RID => gp0_rid ,
- M_AXI_GP0_BRESP => gp0_bresp ,
- M_AXI_GP0_RRESP => gp0_rresp ,
- M_AXI_GP0_RDATA => gp0_rdata ,
-
-
- M_AXI_GP1_ARVALID => gp1_arvalid ,
- M_AXI_GP1_AWVALID => gp1_awvalid ,
- M_AXI_GP1_BREADY => gp1_bready ,
- M_AXI_GP1_RREADY => gp1_rready ,
- M_AXI_GP1_WLAST => gp1_wlast ,
- M_AXI_GP1_WVALID => gp1_wvalid ,
- M_AXI_GP1_ARID => gp1_arid ,
- M_AXI_GP1_AWID => gp1_awid ,
- M_AXI_GP1_WID => gp1_wid ,
- M_AXI_GP1_ARBURST => gp1_arburst ,
- M_AXI_GP1_ARLOCK => gp1_arlock ,
- M_AXI_GP1_ARSIZE => gp1_arsize ,
- M_AXI_GP1_AWBURST => gp1_awburst ,
- M_AXI_GP1_AWLOCK => gp1_awlock ,
- M_AXI_GP1_AWSIZE => gp1_awsize ,
- M_AXI_GP1_ARPROT => gp1_arprot ,
- M_AXI_GP1_AWPROT => gp1_awprot ,
- M_AXI_GP1_ARADDR => gp1_araddr ,
- M_AXI_GP1_AWADDR => gp1_awaddr ,
- M_AXI_GP1_WDATA => gp1_wdata ,
- M_AXI_GP1_ARCACHE => gp1_arcache ,
- M_AXI_GP1_ARLEN => gp1_arlen ,
- M_AXI_GP1_ARQOS => gp1_arqos ,
- M_AXI_GP1_AWCACHE => gp1_awcache ,
- M_AXI_GP1_AWLEN => gp1_awlen ,
- M_AXI_GP1_AWQOS => gp1_awqos ,
- M_AXI_GP1_WSTRB => gp1_wstrb ,
- M_AXI_GP1_ACLK => gp01_aclk ,
- M_AXI_GP1_ARREADY => gp1_arready ,
- M_AXI_GP1_AWREADY => gp1_awready ,
- M_AXI_GP1_BVALID => gp1_bvalid ,
- M_AXI_GP1_RLAST => gp1_rlast ,
- M_AXI_GP1_RVALID => gp1_rvalid ,
- M_AXI_GP1_WREADY => gp1_wready ,
- M_AXI_GP1_BID => gp1_bid ,
- M_AXI_GP1_RID => gp1_rid ,
- M_AXI_GP1_BRESP => gp1_bresp ,
- M_AXI_GP1_RRESP => gp1_rresp ,
- M_AXI_GP1_RDATA => gp1_rdata ,
+ M_AXI_GP0_ARVALID => gp0_arvalid,
+ M_AXI_GP0_AWVALID => gp0_awvalid,
+ M_AXI_GP0_BREADY => gp0_bready,
+ M_AXI_GP0_RREADY => gp0_rready,
+ M_AXI_GP0_WLAST => gp0_wlast,
+ M_AXI_GP0_WVALID => gp0_wvalid,
+ M_AXI_GP0_ARID => gp0_arid,
+ M_AXI_GP0_AWID => gp0_awid,
+ M_AXI_GP0_WID => gp0_wid,
+ M_AXI_GP0_ARBURST => gp0_arburst,
+ M_AXI_GP0_ARLOCK => gp0_arlock,
+ M_AXI_GP0_ARSIZE => gp0_arsize,
+ M_AXI_GP0_AWBURST => gp0_awburst,
+ M_AXI_GP0_AWLOCK => gp0_awlock,
+ M_AXI_GP0_AWSIZE => gp0_awsize,
+ M_AXI_GP0_ARPROT => gp0_arprot,
+ M_AXI_GP0_AWPROT => gp0_awprot,
+ M_AXI_GP0_ARADDR => gp0_araddr,
+ M_AXI_GP0_AWADDR => gp0_awaddr,
+ M_AXI_GP0_WDATA => gp0_wdata,
+ M_AXI_GP0_ARCACHE => gp0_arcache,
+ M_AXI_GP0_ARLEN => gp0_arlen,
+ M_AXI_GP0_ARQOS => gp0_arqos,
+ M_AXI_GP0_AWCACHE => gp0_awcache,
+ M_AXI_GP0_AWLEN => gp0_awlen,
+ M_AXI_GP0_AWQOS => gp0_awqos,
+ M_AXI_GP0_WSTRB => gp0_wstrb,
+ M_AXI_GP0_ACLK => gp01_aclk,
+ M_AXI_GP0_ARREADY => gp0_arready,
+ M_AXI_GP0_AWREADY => gp0_awready,
+ M_AXI_GP0_BVALID => gp0_bvalid,
+ M_AXI_GP0_RLAST => gp0_rlast,
+ M_AXI_GP0_RVALID => gp0_rvalid,
+ M_AXI_GP0_WREADY => gp0_wready,
+ M_AXI_GP0_BID => gp0_bid,
+ M_AXI_GP0_RID => gp0_rid,
+ M_AXI_GP0_BRESP => gp0_bresp,
+ M_AXI_GP0_RRESP => gp0_rresp,
+ M_AXI_GP0_RDATA => gp0_rdata,
+
+
+ M_AXI_GP1_ARVALID => gp1_arvalid,
+ M_AXI_GP1_AWVALID => gp1_awvalid,
+ M_AXI_GP1_BREADY => gp1_bready,
+ M_AXI_GP1_RREADY => gp1_rready,
+ M_AXI_GP1_WLAST => gp1_wlast,
+ M_AXI_GP1_WVALID => gp1_wvalid,
+ M_AXI_GP1_ARID => gp1_arid,
+ M_AXI_GP1_AWID => gp1_awid,
+ M_AXI_GP1_WID => gp1_wid,
+ M_AXI_GP1_ARBURST => gp1_arburst,
+ M_AXI_GP1_ARLOCK => gp1_arlock,
+ M_AXI_GP1_ARSIZE => gp1_arsize,
+ M_AXI_GP1_AWBURST => gp1_awburst,
+ M_AXI_GP1_AWLOCK => gp1_awlock,
+ M_AXI_GP1_AWSIZE => gp1_awsize,
+ M_AXI_GP1_ARPROT => gp1_arprot,
+ M_AXI_GP1_AWPROT => gp1_awprot,
+ M_AXI_GP1_ARADDR => gp1_araddr,
+ M_AXI_GP1_AWADDR => gp1_awaddr,
+ M_AXI_GP1_WDATA => gp1_wdata,
+ M_AXI_GP1_ARCACHE => gp1_arcache,
+ M_AXI_GP1_ARLEN => gp1_arlen,
+ M_AXI_GP1_ARQOS => gp1_arqos,
+ M_AXI_GP1_AWCACHE => gp1_awcache,
+ M_AXI_GP1_AWLEN => gp1_awlen,
+ M_AXI_GP1_AWQOS => gp1_awqos,
+ M_AXI_GP1_WSTRB => gp1_wstrb,
+ M_AXI_GP1_ACLK => gp01_aclk,
+ M_AXI_GP1_ARREADY => gp1_arready,
+ M_AXI_GP1_AWREADY => gp1_awready,
+ M_AXI_GP1_BVALID => gp1_bvalid,
+ M_AXI_GP1_RLAST => gp1_rlast,
+ M_AXI_GP1_RVALID => gp1_rvalid,
+ M_AXI_GP1_WREADY => gp1_wready,
+ M_AXI_GP1_BID => gp1_bid,
+ M_AXI_GP1_RID => gp1_rid,
+ M_AXI_GP1_BRESP => gp1_bresp,
+ M_AXI_GP1_RRESP => gp1_rresp,
+ M_AXI_GP1_RDATA => gp1_rdata,
S_AXI_HP0_ACLK => hp0_aclk,
S_AXI_HP0_ARADDR => hp0_araddr,
@@ -470,7 +470,7 @@ begin
);
- vnc_hw_i: entity work.vnc_hw
+ vnc_hw_i : entity work.vnc_hw
generic map (
video_width => video_width
)
@@ -480,14 +480,14 @@ begin
vnc_data => vnc_data,
vnc_index => vnc_index,
- sys_rst_n => sys_rst_n,
+ sys_rst_n => sys_rst_n,
run => run,
- clk_50m => clk_50m_ps,
+ clk_50m => clk_50m_ps,
- axi_aclk => hp0_aclk,
- axi_aresetn => hp0_nrst,
+ axi_aclk => hp0_aclk,
+ axi_aresetn => hp0_nrst,
axi_awaddr => hp0_awaddr,
axi_awvalid => hp0_awvalid,
@@ -498,108 +498,109 @@ begin
axi_wready => hp0_wready,
axi_bvalid => hp0_bvalid,
axi_bready => hp0_bready
- );
+ );
- fb_hw_i: entity work.fb_hw
+ fb_hw_i : entity work.fb_hw
generic map (
addr_width => addr_width
)
- port map (
- s_axi_aclk => gp01_aclk,
- s_axi_aresetn => gp01_nrst,
-
- s_axi_awid => gp0_awid ,
- s_axi_awaddr => gp0_awaddr,
- s_axi_awlen => gp0_awlen ,
- s_axi_awsize => gp0_awsize ,
- s_axi_awburst => gp0_awburst ,
- s_axi_awlock => gp0_awlock ,
- s_axi_awcache => gp0_awcache ,
- s_axi_awprot => gp0_awprot ,
- s_axi_awvalid => gp0_awvalid ,
- s_axi_awready => gp0_awready ,
- s_axi_wdata => gp0_wdata ,
- s_axi_wstrb => gp0_wstrb ,
- s_axi_wlast => gp0_wlast ,
- s_axi_wvalid => gp0_wvalid ,
- s_axi_wready => gp0_wready ,
- s_axi_bid => gp0_bid ,
- s_axi_bresp => gp0_bresp ,
- s_axi_bvalid => gp0_bvalid ,
- s_axi_bready => gp0_bready ,
- s_axi_arid => gp0_arid ,
- s_axi_araddr => gp0_araddr,
- s_axi_arlen => gp0_arlen,
- s_axi_arsize => gp0_arsize ,
- s_axi_arburst => gp0_arburst ,
- s_axi_arlock => gp0_arlock ,
- s_axi_arcache => gp0_arcache ,
- s_axi_arprot => gp0_arprot ,
- s_axi_arvalid => gp0_arvalid ,
- s_axi_arready => gp0_arready ,
- s_axi_rid => gp0_rid ,
- s_axi_rdata => gp0_rdata ,
- s_axi_rresp => gp0_rresp ,
- s_axi_rlast => gp0_rlast ,
- s_axi_rvalid => gp0_rvalid ,
- s_axi_rready => gp0_rready ,
- overlay_clk => overlay_clk,
- overlay_addr => overlay_addr,
- overlay_gate => overlay_gate,
- overlay_r => overlay_r,
- overlay_g =>overlay_g,
- overlay_b => overlay_b
-);
-
-
- kbd_uarts_i: entity work.kbd_uarts
- port map (
- s_axi_aclk => gp01_aclk,
- s_axi_aresetn => gp01_nrst,
-
- s_axi_awid => gp1_awid ,
- s_axi_awaddr => gp1_awaddr,
- s_axi_awlen => gp1_awlen ,
- s_axi_awsize => gp1_awsize ,
- s_axi_awburst => gp1_awburst ,
- s_axi_awlock => gp1_awlock ,
- s_axi_awcache => gp1_awcache ,
- s_axi_awprot => gp1_awprot ,
- s_axi_awvalid => gp1_awvalid ,
- s_axi_awready => gp1_awready ,
- s_axi_wdata => gp1_wdata ,
- s_axi_wstrb => gp1_wstrb ,
- s_axi_wlast => gp1_wlast ,
- s_axi_wvalid => gp1_wvalid ,
- s_axi_wready => gp1_wready ,
- s_axi_bid => gp1_bid ,
- s_axi_bresp => gp1_bresp ,
- s_axi_bvalid => gp1_bvalid ,
- s_axi_bready => gp1_bready ,
- s_axi_arid => gp1_arid ,
- s_axi_araddr => gp1_araddr,
- s_axi_arlen => gp1_arlen,
- s_axi_arsize => gp1_arsize ,
- s_axi_arburst => gp1_arburst ,
- s_axi_arlock => gp1_arlock ,
- s_axi_arcache => gp1_arcache ,
- s_axi_arprot => gp1_arprot ,
- s_axi_arvalid => gp1_arvalid ,
- s_axi_arready => gp1_arready ,
- s_axi_rid => gp1_rid ,
- s_axi_rdata => gp1_rdata ,
- s_axi_rresp => gp1_rresp ,
- s_axi_rlast => gp1_rlast ,
- s_axi_rvalid => gp1_rvalid ,
- s_axi_rready => gp1_rready ,
-
-u0_tx => u0_tx,
-u0_rx => u0_rx,
-
-u1_tx => u1_tx,
-u1_rx => u1_rx
-);
+ port map (
+ s_axi_aclk => gp01_aclk,
+ s_axi_aresetn => gp01_nrst,
+
+ s_axi_awid => gp0_awid,
+ s_axi_awaddr => gp0_awaddr,
+ s_axi_awlen => gp0_awlen,
+ s_axi_awsize => gp0_awsize,
+ s_axi_awburst => gp0_awburst,
+ s_axi_awlock => gp0_awlock,
+ s_axi_awcache => gp0_awcache,
+ s_axi_awprot => gp0_awprot,
+ s_axi_awvalid => gp0_awvalid,
+ s_axi_awready => gp0_awready,
+ s_axi_wdata => gp0_wdata,
+ s_axi_wstrb => gp0_wstrb,
+ s_axi_wlast => gp0_wlast,
+ s_axi_wvalid => gp0_wvalid,
+ s_axi_wready => gp0_wready,
+ s_axi_bid => gp0_bid,
+ s_axi_bresp => gp0_bresp,
+ s_axi_bvalid => gp0_bvalid,
+ s_axi_bready => gp0_bready,
+ s_axi_arid => gp0_arid,
+ s_axi_araddr => gp0_araddr,
+ s_axi_arlen => gp0_arlen,
+ s_axi_arsize => gp0_arsize,
+ s_axi_arburst => gp0_arburst,
+ s_axi_arlock => gp0_arlock,
+ s_axi_arcache => gp0_arcache,
+ s_axi_arprot => gp0_arprot,
+ s_axi_arvalid => gp0_arvalid,
+ s_axi_arready => gp0_arready,
+ s_axi_rid => gp0_rid,
+ s_axi_rdata => gp0_rdata,
+ s_axi_rresp => gp0_rresp,
+ s_axi_rlast => gp0_rlast,
+ s_axi_rvalid => gp0_rvalid,
+ s_axi_rready => gp0_rready,
+ overlay_clk => overlay_clk,
+ overlay_addr => overlay_addr,
+ overlay_gate => overlay_gate,
+ overlay_r => overlay_r,
+ overlay_g => overlay_g,
+ overlay_b => overlay_b
+ );
+
+
+ kbd_uarts_i : entity work.kbd_uarts
+ port map (
+ s_axi_aclk => gp01_aclk,
+ s_axi_aresetn => gp01_nrst,
+
+ s_axi_arvalid => gp1_arvalid,
+ s_axi_awvalid => gp1_awvalid,
+ s_axi_bready => gp1_bready,
+ s_axi_rready => gp1_rready,
+ s_axi_wlast => gp1_wlast,
+ s_axi_wvalid => gp1_wvalid,
+ s_axi_arid => gp1_arid,
+ s_axi_awid => gp1_awid,
+ s_axi_arburst => gp1_arburst,
+ s_axi_arlock => gp1_arlock,
+ s_axi_arsize => gp1_arsize,
+ s_axi_awburst => gp1_awburst,
+ s_axi_awlock => gp1_awlock,
+ s_axi_awsize => gp1_awsize,
+ s_axi_arprot => gp1_arprot,
+ s_axi_awprot => gp1_awprot,
+ s_axi_araddr => gp1_araddr,
+ s_axi_awaddr => gp1_awaddr,
+ s_axi_wdata => gp1_wdata,
+ s_axi_arcache => gp1_arcache,
+ s_axi_arlen => gp1_arlen,
+ s_axi_arqos => gp1_arqos,
+ s_axi_awcache => gp1_awcache,
+ s_axi_awlen => gp1_awlen,
+ s_axi_awqos => gp1_awqos,
+ s_axi_wstrb => gp1_wstrb,
+ s_axi_arready => gp1_arready,
+ s_axi_awready => gp1_awready,
+ s_axi_bvalid => gp1_bvalid,
+ s_axi_rlast => gp1_rlast,
+ s_axi_rvalid => gp1_rvalid,
+ s_axi_wready => gp1_wready,
+ s_axi_bid => gp1_bid,
+ s_axi_rid => gp1_rid,
+ s_axi_bresp => gp1_bresp,
+ s_axi_rresp => gp1_rresp,
+ s_axi_rdata => gp1_rdata,
+
+ u0_tx => u0_tx,
+ u0_rx => u0_rx,
+ u1_tx => u1_tx,
+ u1_rx => u1_rx
+ );
generated by cgit v1.2.3 (git 2.25.1) at 2025-11-17 20:41:34 +0000