diff options
Diffstat (limited to 'fpga/hp_lcd_driver/common.vhdl')
| -rw-r--r-- | fpga/hp_lcd_driver/common.vhdl | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl index a3e41d4..cfe3143 100644 --- a/fpga/hp_lcd_driver/common.vhdl +++ b/fpga/hp_lcd_driver/common.vhdl @@ -44,12 +44,12 @@ entity common is video_out_valid : out std_logic; video_out_clk : out std_logic; video_out_index : out std_logic; - video_in_addr : out std_logic_vector(addr_width-1 downto 0); - video_in_clk : out std_logic; - video_in_gate : in std_logic; - video_in_r : in std_logic_vector(7 downto 0); - video_in_g : in std_logic_vector(7 downto 0); - video_in_b : in std_logic_vector(7 downto 0) + video_in_addr : out std_logic_vector(addr_width-1 downto 0); + video_in_clk : out std_logic; + video_in_gate : in std_logic; + video_in_r : in std_logic_vector(7 downto 0); + video_in_g : in std_logic_vector(7 downto 0); + video_in_b : in std_logic_vector(7 downto 0) ); end common; @@ -65,9 +65,9 @@ architecture Behavioral of common is signal rd_addr : std_logic_vector(addr_width-1 downto 0); signal rd_data : std_logic_vector(video_width-1 downto 0); - signal r : std_logic_vector(7 downto 0); - signal g : std_logic_vector(7 downto 0); - signal b : std_logic_vector(7 downto 0); + signal r : std_logic_vector(7 downto 0); + signal g : std_logic_vector(7 downto 0); + signal b : std_logic_vector(7 downto 0); signal r_s : std_logic_vector(7 downto 0); signal g_s : std_logic_vector(7 downto 0); signal b_s : std_logic_vector(7 downto 0); @@ -251,28 +251,28 @@ begin rd_data => rd_data ); - video_in_addr <= rd_addr; - video_in_clk <= o_clk; + video_in_addr <= rd_addr; + video_in_clk <= o_clk; r_s <= x"ff" when rd_data(0) = '1' else - x"00"; + x"00"; g_s <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else - x"80" when rd_data(1) = '1' else - x"00"; + x"80" when rd_data(1) = '1' else + x"00"; b_s <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else - x"80" when rd_data(2) = '1' else - x"00"; + x"80" when rd_data(2) = '1' else + x"00"; r <= r_s when video_in_gate = '0' else - video_in_r; + video_in_r; g <= g_s when video_in_gate = '0' else - video_in_g; + video_in_g; b <= b_s when video_in_gate = '0' else - video_in_b; + video_in_b; output0 : entity work.output_stage |