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-rw-r--r--fpga/hp_lcd_driver/.gitignore1
-rw-r--r--fpga/hp_lcd_driver/Makefile9
-rw-r--r--fpga/hp_lcd_driver/artix7.mk3
-rw-r--r--fpga/hp_lcd_driver/clkgen_zynq7.vhdl65
-rw-r--r--fpga/hp_lcd_driver/ebaz4205.mk2
-rw-r--r--fpga/hp_lcd_driver/ebaz4205.tcl6
-rw-r--r--fpga/hp_lcd_driver/ebaz4205.xdc138
-rw-r--r--fpga/hp_lcd_driver/fifo_to_axi.vhdl112
-rw-r--r--fpga/hp_lcd_driver/zynq7.mk56
-rw-r--r--fpga/hp_lcd_driver/zynq7_config.tcl30
-rw-r--r--fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl87
-rw-r--r--fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl33
-rw-r--r--fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl40
-rw-r--r--fpga/hp_lcd_driver/zynq_wrapper.vhdl291
14 files changed, 868 insertions, 5 deletions
diff --git a/fpga/hp_lcd_driver/.gitignore b/fpga/hp_lcd_driver/.gitignore
index 4284f6d..4b83774 100644
--- a/fpga/hp_lcd_driver/.gitignore
+++ b/fpga/hp_lcd_driver/.gitignore
@@ -7,3 +7,4 @@ NOT/
*.swp
*.lic
*.orig
+build_ebaz4205
diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 458951d..5089f5c 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,8 +1,11 @@
-TARGETS= rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415
+TARGETS= ebaz4205 #rando_a7 #smh-ac415b #spartan6 #ep4ce6 smh-ac415
#fish:smh-ac415
-better_default: build_rando_a7/hp_lcd_driver.svf
- ./prog_a7
+#better_default: build_rando_a7/hp_lcd_driver.svf
+# ./prog_a7
+
+better_default: build_ebaz4205/out/hp_lcd_driver.bin
+ scp build_ebaz4205/out/hp_lcd_driver.bin 10.16.66.163:/boot/uboot/hp_lcd_driver.bin
default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
index 8c83e78..8c3245b 100644
--- a/fpga/hp_lcd_driver/artix7.mk
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -30,8 +30,7 @@ SRCS= ${IP} \
tmds_encode.vhdl \
tmds_output_artix7.vhdl \
tmds_phy_artix7.vhdl \
- vram_artix7.vhdl
-
+ vram_artix7.vhdl
OPENOCD=openocd -f openocd/${BOARD}.cfg
diff --git a/fpga/hp_lcd_driver/clkgen_zynq7.vhdl b/fpga/hp_lcd_driver/clkgen_zynq7.vhdl
new file mode 100644
index 0000000..d87cbaf
--- /dev/null
+++ b/fpga/hp_lcd_driver/clkgen_zynq7.vhdl
@@ -0,0 +1,65 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity clkgen is
+ port (
+ sys_rst_n : in std_logic;
+ clk_in : in std_logic;
+ i_clk : out std_logic;
+ o_clk : out std_logic;
+ o_clk_x2 : out std_logic;
+ o_clk_phy : out std_logic;
+ locked : out std_logic
+ );
+end clkgen;
+architecture Behavioural of clkgen is
+
+ signal clk_240m : std_logic;
+ signal clk_78_571m : std_logic;
+ signal clk_80m : std_logic;
+ signal clk_24m : std_logic;
+ signal clk_48m : std_logic;
+ signal clk_50m : std_logic;
+
+ signal reset : std_logic;
+begin
+
+ reset <= not sys_rst_n;
+
+ o_clk_buf : BUFG port map (
+ I => clk_in,
+ O => clk_50m);
+
+--
+-- mmcm_0_i : mmcm_0 port map (
+-- clk_in1 => clk_50m,
+-- clk_out1 => clk_240m,
+-- clk_out2 => clk_80m,
+-- clk_out3 => clk_48m,
+-- clk_out4 => clk_24m,
+-- reset => reset,
+-- locked => locked
+-- );
+--
+-- mmcm_1_i : mmcm_1 port map (
+-- clk_in1 => clk_50m,
+-- clk_out1 => clk_78_571m,
+-- reset => reset
+-- );
+--
+-- o_clk_phy <= clk_240m;
+-- o_clk <= clk_24m;
+-- o_clk_x2 <= clk_48m;
+-- i_clk <= clk_78_571m;
+
+ o_clk_phy <= clk_in;
+ o_clk <= clk_in;
+ o_clk_x2 <= clk_in;
+ i_clk <= clk_in;
+
+end Behavioural;
diff --git a/fpga/hp_lcd_driver/ebaz4205.mk b/fpga/hp_lcd_driver/ebaz4205.mk
new file mode 100644
index 0000000..e6921b5
--- /dev/null
+++ b/fpga/hp_lcd_driver/ebaz4205.mk
@@ -0,0 +1,2 @@
+BOARD=ebaz4205
+include zynq7.mk
diff --git a/fpga/hp_lcd_driver/ebaz4205.tcl b/fpga/hp_lcd_driver/ebaz4205.tcl
new file mode 100644
index 0000000..74b9e4d
--- /dev/null
+++ b/fpga/hp_lcd_driver/ebaz4205.tcl
@@ -0,0 +1,6 @@
+#
+set part_num "xc7z010clg400-1"
+set normal_xdc "../ebaz4205.xdc"
+set use_pclk 1
+set input_video_width 8
+set video_width 6
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
new file mode 100644
index 0000000..903334c
--- /dev/null
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -0,0 +1,138 @@
+# "Normal" constraints file- not early not late
+
+set_property PACKAGE_PIN U18 [get_ports {eth0_clk_o}]
+
+set_property PACKAGE_PIN U15 [get_ports {eth0_gmii_tx_clk_i}]
+set_property PACKAGE_PIN W19 [get_ports {eth0_gmii_tx_en_o[0]}]
+set_property PACKAGE_PIN W18 [get_ports {eth0_gmii_txd_o[0]}]
+set_property PACKAGE_PIN Y18 [get_ports {eth0_gmii_txd_o[1]}]
+set_property PACKAGE_PIN V18 [get_ports {eth0_gmii_txd_o[2]}]
+set_property PACKAGE_PIN Y19 [get_ports {eth0_gmii_txd_o[3]}]
+
+set_property PACKAGE_PIN U14 [get_ports {eth0_gmii_rx_clk_i}]
+set_property PACKAGE_PIN W16 [get_ports {eth0_gmii_rx_dv_i}]
+set_property PACKAGE_PIN Y16 [get_ports {eth0_gmii_rxd_i[0]}]
+set_property PACKAGE_PIN V16 [get_ports {eth0_gmii_rxd_i[1]}]
+set_property PACKAGE_PIN V17 [get_ports {eth0_gmii_rxd_i[2]}]
+set_property PACKAGE_PIN Y17 [get_ports {eth0_gmii_rxd_i[3]}]
+
+
+set_property PACKAGE_PIN W15 [get_ports {eth0_mdio_mdc_o}]
+set_property PACKAGE_PIN Y14 [get_ports {eth0_mdio_mdio_io}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports eth0_*]
+
+set_property PACKAGE_PIN W13 [get_ports {green_led}]
+set_property PACKAGE_PIN W14 [get_ports {red_led}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports *_led]
+
+
+#set_property IOSTANDARD LVCMOS33 [get_ports clk_50m]
+#set_property PACKAGE_PIN R4 [get_ports clk_50m]
+
+#set_property PACKAGE_PIN T1 [get_ports {led_1}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
+
+#set_property PACKAGE_PIN U3 [get_ports {hdmi_r_p}]
+#set_property PACKAGE_PIN V3 [get_ports {hdmi_r_n}]
+#set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}]
+#set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}]
+#set_property PACKAGE_PIN R3 [get_ports {hdmi_b_p}]
+#set_property PACKAGE_PIN R2 [get_ports {hdmi_b_n}]
+#set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}]
+#set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}]
+#
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
+#
+##set_property DRIVE 16 [get_ports {hdmi_c_p}]
+##set_property DRIVE 16 [get_ports {hdmi_c_n}]
+##set_property DRIVE 16 [get_ports {hdmi_r_p}]
+##set_property DRIVE 16 [get_ports {hdmi_r_n}]
+##set_property DRIVE 16 [get_ports {hdmi_g_p}]
+##set_property DRIVE 16 [get_ports {hdmi_g_n}]
+##set_property DRIVE 16 [get_ports {hdmi_b_p}]
+#
+#set_property PACKAGE_PIN W1 [get_ports {hdmi_vcc}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
+#
+#
+##set_property PACKAGE_PIN P20 [get_ports rxd]
+##set_property PACKAGE_PIN T20 [get_ports txd]
+##set_property IOSTANDARD LVCMOS33 [get_ports rxd]
+##set_property IOSTANDARD LVCMOS33 [get_ports txd]
+#
+##set_property PACKAGE_PIN T3 [get_ports key]
+##set_property IOSTANDARD LVCMOS33 [get_ports key]
+#
+#set_property PACKAGE_PIN N22 [get_ports {video[0]}]
+#set_property PACKAGE_PIN N20 [get_ports {video[1]}]
+#set_property PACKAGE_PIN N18 [get_ports {video[2]}]
+#set_property PACKAGE_PIN K18 [get_ports {video[3]}]
+#set_property PACKAGE_PIN M18 [get_ports {video[4]}]
+#set_property PACKAGE_PIN M15 [get_ports {video[5]}]
+#set_property PACKAGE_PIN U20 [get_ports {video[6]}]
+#set_property PACKAGE_PIN T21 [get_ports {video[7]}]
+#
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
+#
+#set_property PACKAGE_PIN W19 [get_ports {pclk_in}]
+#set_property PACKAGE_PIN R18 [get_ports {vsync_in}]
+#set_property PACKAGE_PIN Y18 [get_ports {hsync_in}]
+#set_property PACKAGE_PIN P16 [get_ports {r_out}]
+#set_property PACKAGE_PIN V18 [get_ports {g_out}]
+#set_property PACKAGE_PIN P15 [get_ports {b_out}]
+#set_property PACKAGE_PIN P14 [get_ports {i_clk_out}]
+#set_property PACKAGE_PIN V17 [get_ports {hsync_out}]
+#set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
+#
+#
+#set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {r_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {g_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {b_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}]
+#
+#set_property PACKAGE_PIN AA18 [get_ports {sys_rst_n}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sys_rst_n}]
+#set_property PULLTYPE PULLUP [get_ports {sys_rst_n}]
+#
+#create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m]
+##set_false_path -from [get_ports pci_exp_rst_n]
+
+
+###############################################################################
+# Additional design / project settings
+###############################################################################
+
+# Power down on overtemp
+set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
+set_property BITSTREAM.CONFIG.USERID 32'hf00dbabe [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+
+
+
diff --git a/fpga/hp_lcd_driver/fifo_to_axi.vhdl b/fpga/hp_lcd_driver/fifo_to_axi.vhdl
new file mode 100644
index 0000000..6129f50
--- /dev/null
+++ b/fpga/hp_lcd_driver/fifo_to_axi.vhdl
@@ -0,0 +1,112 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity fifo_to_axi is
+ generic (
+ ADDR_WIDTH : integer := 32;
+ START : unsigned(31 downto 0) := x"FFFC0000";
+ SIZE : unsigned(31 downto 0) := x"00040000"
+ );
+ port (
+ aclk : in std_logic;
+ aresetn : in std_logic;
+
+ run: in std_logic;
+
+ pointer : out std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+ fifo_empty : in std_logic;
+ fifo_rdata : in std_logic_vector(63 downto 0);
+ fifo_rd_en : out std_logic;
+
+ axi_awaddr : out std_logic_vector (ADDR_WIDTH-1 downto 0);
+ axi_awvalid : out std_logic;
+ axi_awready : in std_logic;
+ axi_wdata : out std_logic_vector (63 downto 0);
+ axi_wstrb : out std_logic_vector (7 downto 0);
+ axi_wvalid : out std_logic;
+ axi_wready : in std_logic;
+ axi_bvalid : in std_logic;
+ axi_bready : out std_logic
+ );
+end entity fifo_to_axi;
+
+architecture Behavioral of fifo_to_axi is
+
+ --signal lazy : std_logic_vector(63 downto 0);
+ signal addr : std_logic_vector(ADDR_WIDTH-1 downto 0) := std_logic_vector(START);
+ signal data : std_logic_vector(63 downto 0);
+ signal do_bus_cycle : std_logic;
+ signal s_run : std_logic;
+
+begin
+
+
+ run_sync : entity work.synchronizer
+ generic map(stages => 2)
+ port map (
+ clk => aclk,
+ i => run,
+ o => s_run
+ );
+
+
+ --lazy <= (ADDR_WIDTH-4 downto 0 => addr(ADDR_WIDTH-1 downto 3), others => '0');
+ --pointer <= lazy(pointer'length -1 downto 0);
+ pointer <= addr;
+
+
+ axi_bready <= do_bus_cycle;
+ axi_wdata <= data;
+ axi_wstrb <= (others => '1');
+ axi_awaddr <= addr;
+
+ --XXX this is moderately budget, it could do with a tonne of pipelining
+
+ process (aclk)
+ begin
+ if rising_edge(aclk) then
+ if aresetn = '0' then
+ axi_awvalid <= '0';
+ axi_wvalid <= '0';
+ do_bus_cycle <= '0';
+ fifo_rd_en <= '0';
+ addr<= std_logic_vector(START);
+ elsif run='1' and do_bus_cycle = '1' then
+ fifo_rd_en <= '0';
+
+ if axi_bvalid = '1' then
+ do_bus_cycle <= '0';
+ if addr = std_logic_vector(START+SIZE-to_unsigned(8,ADDR_WIDTH)) then
+ addr<= std_logic_vector(START);
+ else
+ addr <= std_logic_vector(unsigned(addr) +to_unsigned(8,ADDR_WIDTH));
+ end if;
+ axi_awvalid <= '0';
+ axi_wvalid <= '0';
+ end if;
+ if axi_awready = '1' then
+ axi_awvalid <= '0';
+ end if;
+ if axi_wready = '1' then
+ axi_wvalid <= '0';
+ end if;
+ elsif do_bus_cycle = '0' then
+
+ if fifo_empty = '0' then
+ data <= fifo_rdata;
+ fifo_rd_en <= '1';
+ do_bus_cycle <= '1';
+ axi_awvalid <= '1';
+ axi_wvalid <= '1';
+ end if;
+ end if;
+
+ end if;
+
+ end process;
+
+end Behavioral;
+
+
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
new file mode 100644
index 0000000..d04e7ec
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -0,0 +1,56 @@
+BUILD=build_${BOARD}
+
+IP= \
+ zynq7_ip/blk_mem_gen_0.tcl \
+ zynq7_ip/processing_system7_0.tcl
+
+
+BIT=${BUILD}/out/hp_lcd_driver.bit
+BIN=${BUILD}/out/hp_lcd_driver.bin
+
+IP_STAMP=${IP:zynq7_ip/%.tcl=${BUILD}/ip/%/stamp}
+SRCS= ${IP} \
+ zynq7_config.tcl \
+ zynq7_hp_lcd_driver.tcl \
+ ${BOARD}.tcl \
+ ${BOARD}.xdc \
+ clkgen_zynq7.vhdl \
+ debounce.vhdl \
+ delay.vhdl \
+ edge_det.vhdl \
+ hp_lcd_driver.vhdl \
+ input_formatter.vhdl \
+ input_stage.vhdl \
+ output_analog.vhdl \
+ output_formatter.vhdl \
+ output_stage.vhdl \
+ synchronizer.vhdl \
+ tmds_encoder.vhdl \
+ tmds_encode.vhdl \
+ tmds_output_artix7.vhdl \
+ tmds_phy_artix7.vhdl \
+ vram_artix7.vhdl \
+ zynq_wrapper.vhdl \
+ fifo_to_axi.vhdl
+
+
+
+OPENOCD=openocd -f openocd/${BOARD}.cfg
+
+default: ${BUILD}/build.stamp
+
+${BIN} ${BIT}:${BUILD}/build.stamp
+
+${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
+ mkdir -p ${BUILD}
+ (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../zynq7_hp_lcd_driver.tcl)
+ #scripts/xilinx_bit_to_bin.pl ${BIT} ${BIN}
+ touch $@
+
+${BUILD}/ip/%/stamp:zynq7_ip/%.tcl
+ mkdir -p ${BUILD}/ip
+ /bin/rm -rf $(dir $@)
+ (cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch -source ../$<) && touch $@
+
+
+${BIT}: ${BUILD}/build.stamp
diff --git a/fpga/hp_lcd_driver/zynq7_config.tcl b/fpga/hp_lcd_driver/zynq7_config.tcl
new file mode 100644
index 0000000..d76719c
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_config.tcl
@@ -0,0 +1,30 @@
+#
+set board $::env(BOARD)
+set board_tcl $source_dir/$board.tcl
+set build_dir .
+set ip_dir $build_dir/ip
+set bd_dir $build_dir/bd
+set ipl_dir $build_dir/ip_library
+set output_dir $build_dir/out
+source $board_tcl
+create_project -in_memory -part $part_num
+
+file mkdir $build_dir
+file mkdir $bd_dir
+file mkdir $ip_dir
+file mkdir $ipl_dir
+file mkdir $output_dir
+
+#WARNING: [Vivado 12-13651] The IP file '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0/mmcm_0.xci' has been moved from its original location, as a result the outputs for this IP will now be generated in '/home/root/projects/hp_instrument_lcds/fpga/artix7/build-rando_a7/ip/mmcm_0'. Alternatively a copy of the IP can be imported into the project using one of the 'import_ip' or 'import_files' commands.
+set_msg_config -id 12-13651 -suppress
+
+
+#WARNING: [DRC REQP-1839] RAMB36 async control check: The RAMB36E1 vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B has an input control pin vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.CASCADED_PRIM36.ram_B/ADDRBWRADDR[12] (net: vram0/bmg0/U0/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/addrb[12]) which is driven by a register (output0/output_formatter/addr_reg[12]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default.
+set_msg_config -id REQP-1839 -suppress
+
+
+
+#WARNING: [Synth 8-3848] Net dma_axi_awid in module/entity pcie_tpm_widget does not have driver. [/root/projects/tpm_interposer/logic_analyzer/source/pcie_tpm_widget.vhdl:88]
+#set_msg_config -id 8-3848 -new_severity ERROR
+
+
diff --git a/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
new file mode 100644
index 0000000..2b6d45f
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_hp_lcd_driver.tcl
@@ -0,0 +1,87 @@
+#
+set source_dir [file dirname [file normalize [info script]]]
+
+source $source_dir/zynq7_config.tcl
+
+file mkdir $output_dir
+
+set files [glob -nocomplain "$output_dir/*"]
+if {[llength $files] != 0} {
+ # clear folder contents
+ puts "deleting contents of $output_dir"
+ file delete -force {*}[glob -directory $output_dir *];
+} else {
+ puts "$output_dir is empty"
+}
+
+#Reference HDL and constraint source files
+
+#read_xdc $early_xdc
+
+#read_verilog [ glob ../source/*.v ]
+#read_vhdl -vhdl2008 -library work [ glob ../source/*.vhdl ]
+read_vhdl -vhdl2008 -library work { ../zynq_wrapper.vhdl ../fifo_to_axi.vhdl ../clkgen_zynq7.vhdl ../debounce.vhdl ../delay.vhdl ../edge_det.vhdl ../hp_lcd_driver.vhdl ../input_formatter.vhdl ../input_stage.vhdl ../output_analog.vhdl ../output_formatter.vhdl ../output_stage.vhdl ../synchronizer.vhdl ../tmds_encoder.vhdl ../tmds_encode.vhdl ../tmds_output_artix7.vhdl ../tmds_phy_artix7.vhdl ../vram_artix7.vhdl }
+
+set generics {}
+append generics { } "video_width=$video_width"
+append generics { } "input_video_width=$input_video_width"
+append generics { } "BOARD=\"$board\""
+append generics { } "use_pclk=$use_pclk"
+
+set_property generic "$generics" [current_fileset]
+puts $generics
+
+read_ip $ip_dir/blk_mem_gen_0/blk_mem_gen_0.xci
+read_ip $ip_dir/processing_system7_0/processing_system7_0.xci
+#read_ip $ip_dir/mmcm_0/mmcm_0.xci
+#read_ip $ip_dir/mmcm_1/mmcm_1.xci
+
+read_xdc $normal_xdc
+
+#Run Synthesis
+synth_design -top zynq_wrapper -part $part_num
+write_checkpoint -force $output_dir/post_synth.dcp
+report_timing_summary -file $output_dir/post_synth_timing_summary.rpt
+report_utilization -file $output_dir/post_synth_util.rpt
+
+set crdl [get_param tcl.collectionResultDisplayLimit]
+set_param tcl.collectionResultDisplayLimit 10000000
+
+set f [open "$output_dir/cells.txt" w]
+puts $f [get_cells -hierarchical]
+close $f
+
+set f [open "$output_dir/nets.txt" w]
+puts $f [get_nets -hierarchical]
+close $f
+set_param tcl.collectionResultDisplayLimit $crdl
+
+set f [open "$output_dir/pins.txt" w]
+puts $f [get_pins -hierarchical]
+close $f
+set_param tcl.collectionResultDisplayLimit $crdl
+
+#run optimization
+opt_design
+place_design
+report_clock_utilization -file $output_dir/clock_util.rpt
+
+#get timing violations and run optimizations if needed
+if {[get_property SLACK [get_timing_paths -max_paths 1 -nworst 1 -setup]] < 0} {
+ puts "Found setup timing violations => running physical optimization"
+ phys_opt_design
+}
+write_checkpoint -force $output_dir/post_place.dcp
+report_utilization -file $output_dir/post_place_util.rpt
+report_timing_summary -file $output_dir/post_place_timing_summary.rpt
+
+#Route design and generate bitstream
+route_design -directive Explore
+write_checkpoint -force $output_dir/post_route.dcp
+report_route_status -file $output_dir/post_route_status.rpt
+report_timing_summary -file $output_dir/post_route_timing_summary.rpt
+report_power -file $output_dir/post_route_power.rpt
+report_drc -file $output_dir/post_imp_drc.rpt
+report_io -file $output_dir/post_imp_placed.rpt
+write_verilog -force $output_dir/cpu_impl_netlist.v -mode timesim -sdf_anno true
+write_bitstream -force -bin_file $output_dir/hp_lcd_driver.bit
diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl
new file mode 100644
index 0000000..b3e3dce
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_0.tcl
@@ -0,0 +1,33 @@
+
+
+set source_dir [file dirname [file dirname [file normalize [info script]]]]
+
+source $source_dir/zynq7_config.tcl
+
+create_ip -name blk_mem_gen -vendor xilinx.com -library ip -version 8.4 -module_name blk_mem_gen_0 -dir $ip_dir
+
+set_property -dict [list \
+ CONFIG.Memory_Type {Simple_Dual_Port_RAM} \
+ CONFIG.Enable_32bit_Address {false} \
+ CONFIG.Use_Byte_Write_Enable {false} \
+ CONFIG.Byte_Size {9} \
+ CONFIG.Write_Width_A {6} \
+ CONFIG.Write_Depth_A {245760} \
+ CONFIG.Read_Width_A {6} \
+ CONFIG.Operating_Mode_A {NO_CHANGE} \
+ CONFIG.Write_Width_B {6} \
+ CONFIG.Read_Width_B {6} \
+ CONFIG.Enable_B {Use_ENB_Pin} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Register_PortB_Output_of_Memory_Primitives {true} \
+ CONFIG.Use_RSTB_Pin {false} \
+ CONFIG.Port_B_Clock {22} \
+ CONFIG.Port_B_Enable_Rate {22} \
+ CONFIG.Disable_Collision_Warnings {false} \
+ CONFIG.EN_SAFETY_CKT {false} \
+ ] [get_ips blk_mem_gen_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips]
+
diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
new file mode 100644
index 0000000..67c5eda
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
@@ -0,0 +1,40 @@
+set source_dir [file dirname [file dirname [file normalize [info script]]]]
+
+source $source_dir/zynq7_config.tcl
+
+create_ip -name processing_system7 -vendor xilinx.com -library ip -version 5.5 -module_name processing_system7_0 -dir $ip_dir
+
+
+set_property -dict [list \
+ CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {20} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {250} \
+ CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {100} \
+ CONFIG.PCW_USE_S_AXI_HP0 {1} \
+ CONFIG.PCW_USE_HIGH_OCM {1} \
+ CONFIG.PCW_EN_CLK1_PORT {1} \
+ CONFIG.PCW_EN_CLK2_PORT {1} \
+ CONFIG.PCW_EN_RST1_PORT {1} \
+ CONFIG.PCW_EN_RST2_PORT {1} \
+ CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \
+ CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \
+ CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_NAND_NAND_IO {MIO 0 2.. 14} \
+ CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_ENET0_ENET0_IO {EMIO} \
+ CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
+ CONFIG.PCW_ENET0_GRP_MDIO_IO {EMIO} \
+ CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_UART1_UART1_IO {MIO 24 .. 25} \
+ CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} \
+ CONFIG.PCW_I2C0_I2C0_IO {MIO 26 .. 27} \
+ CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+ CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {100 Mbps}] [get_ips processing_system7_0]
+
+generate_target all [get_ips]
+
+synth_ip [get_ips]
+
diff --git a/fpga/hp_lcd_driver/zynq_wrapper.vhdl b/fpga/hp_lcd_driver/zynq_wrapper.vhdl
new file mode 100644
index 0000000..4323aca
--- /dev/null
+++ b/fpga/hp_lcd_driver/zynq_wrapper.vhdl
@@ -0,0 +1,291 @@
+--------------------------------------------------------------------------------
+-- Copyright (C) 2020 - embed-me
+--
+-- Lukas Lichtl <support@embed-me.com>
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License v2 as published by
+-- the Free Software Foundation.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+-- Function description:
+--
+--------------------------------------------------------------------------------
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+entity zynq_wrapper is
+
+ port (
+ -- ddr
+ ddr_addr_io : inout std_logic_vector (14 downto 0);
+ ddr_ba_io : inout std_logic_vector (2 downto 0);
+ ddr_cas_n_io : inout std_logic;
+ ddr_ck_n_io : inout std_logic;
+ ddr_ck_p_io : inout std_logic;
+ ddr_cke_io : inout std_logic;
+ ddr_cs_n_io : inout std_logic;
+ ddr_dm_io : inout std_logic_vector (3 downto 0);
+ ddr_dq_io : inout std_logic_vector (31 downto 0);
+ ddr_dqs_n_io : inout std_logic_vector (3 downto 0);
+ ddr_dqs_p_io : inout std_logic_vector (3 downto 0);
+ ddr_odt_io : inout std_logic;
+ ddr_ras_n_io : inout std_logic;
+ ddr_reset_n_io : inout std_logic;
+ ddr_we_n_io : inout std_logic;
+ -- eth0
+ eth0_clk_o : out std_logic; -- alternative clock, only used when Oscillator is missing on the PCB
+ eth0_gmii_rx_clk_i : in std_logic;
+ eth0_gmii_rx_dv_i : in std_logic;
+ eth0_gmii_rxd_i : in std_logic_vector (3 downto 0);
+ eth0_gmii_tx_clk_i : in std_logic;
+ eth0_gmii_tx_en_o : out std_logic_vector (0 to 0);
+ eth0_gmii_txd_o : out std_logic_vector (3 downto 0);
+ eth0_mdio_mdc_o : out std_logic;
+ eth0_mdio_mdio_io : inout std_logic;
+ -- ios
+ fixed_io_ddr_vrn_io : inout std_logic;
+ fixed_io_ddr_vrp_io : inout std_logic;
+ fixed_io_mio_io : inout std_logic_vector (53 downto 0);
+ fixed_io_ps_clk_io : inout std_logic;
+ fixed_io_ps_porb_io : inout std_logic;
+ fixed_io_ps_srstb_io : inout std_logic;
+ green_led : out std_logic;
+ red_led : out std_logic);
+
+end entity zynq_wrapper;
+
+
+
+architecture arch of zynq_wrapper is
+
+ signal eth0_gmii_txd : std_logic_vector(7 downto 0);
+ signal eth0_gmii_rxd : std_logic_vector(7 downto 0);
+
+ signal emio_i : std_logic_vector(63 downto 0);
+ signal emio_o : std_logic_vector(63 downto 0);
+ signal emio_t : std_logic_vector(63 downto 0);
+
+
+
+signal gp0_aclk:std_logic;
+signal gp0_nrst:std_logic;
+
+signal hp0_aclk:std_logic;
+signal hp0_nrst:std_logic;
+signal hp0_arvalid:std_logic;
+signal hp0_araddr:std_logic_vector(31 downto 0);
+signal hp0_arready:std_logic;
+signal hp0_awaddr:std_logic_vector(31 downto 0);
+signal hp0_awready:std_logic;
+signal hp0_awvalid:std_logic;
+signal hp0_bready:std_logic;
+signal hp0_bvalid:std_logic;
+signal hp0_rdata:std_logic_vector(63 downto 0);
+signal hp0_wdata:std_logic_vector(63 downto 0);
+signal hp0_rready:std_logic;
+signal hp0_rvalid:std_logic;
+signal hp0_wready:std_logic;
+signal hp0_wvalid:std_logic;
+signal hp0_wstrb:std_logic_vector(7 downto 0);
+
+signal tc:natural;
+signal dowrite:std_logic;
+
+signal fifo_pointer:std_logic_vector(31 downto 0);
+signal fifo_data:std_logic_vector(63 downto 0);
+
+signal run:std_logic;
+
+signal eth0_mdio_mdio_i:std_logic;
+signal eth0_mdio_mdio_o:std_logic;
+Signal eth0_mdio_mdio_t:std_logic;
+
+
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- Component Instatiations
+ -----------------------------------------------------------------------------
+
+ processing_system7_0_i : entity work.processing_system7_0
+ port map (
+ DDR_Addr => ddr_addr_io,
+ DDR_BankAddr => ddr_ba_io,
+ DDR_CAS_n => ddr_cas_n_io,
+ DDR_Clk_n => ddr_ck_n_io,
+ DDR_Clk => ddr_ck_p_io,
+ DDR_CKE => ddr_cke_io,
+ DDR_CS_n => ddr_cs_n_io,
+ DDR_DM => ddr_dm_io,
+ DDR_DQ => ddr_dq_io,
+ DDR_DQS_n => ddr_dqs_n_io,
+ DDR_DQS => ddr_dqs_p_io,
+ DDR_ODT => ddr_odt_io,
+ DDR_RAS_n => ddr_ras_n_io,
+ DDR_DRSTB => ddr_reset_n_io,
+ DDR_WEB => ddr_we_n_io,
+ FCLK_CLK0 => eth0_clk_o,
+ FCLK_CLK1 => gp0_aclk,
+ FCLK_CLK2 => hp0_aclk,
+ FCLK_RESET1_N => gp0_nrst,
+ FCLK_RESET2_N => hp0_nrst,
+
+ ENET0_GMII_RX_CLK => eth0_gmii_rx_clk_i,
+ ENET0_GMII_RX_DV => eth0_gmii_rx_dv_i,
+ ENET0_GMII_RXD => eth0_gmii_rxd,
+ ENET0_GMII_RX_ER => '0',
+
+ ENET0_GMII_TX_CLK => eth0_gmii_tx_clk_i,
+ ENET0_GMII_TX_EN => eth0_gmii_tx_en_o,
+ ENET0_GMII_TXD => eth0_gmii_txd,
+
+ ENET0_MDIO_MDC => eth0_mdio_mdc_o,
+ ENET0_MDIO_O => eth0_mdio_mdio_o,
+ ENET0_MDIO_I => eth0_mdio_mdio_i,
+ ENET0_MDIO_T => eth0_mdio_mdio_t,
+ DDR_VRN => fixed_io_ddr_vrn_io,
+ DDR_VRP => fixed_io_ddr_vrp_io,
+ MIO(53 downto 0) => fixed_io_mio_io,
+ PS_CLK => fixed_io_ps_clk_io,
+ PS_PORB => fixed_io_ps_porb_io,
+ PS_SRSTB => fixed_io_ps_srstb_io,
+ GPIO_I => emio_i,
+ GPIO_O => emio_o,
+ GPIO_T => emio_t,
+
+ M_AXI_GP0_ACLK => gp0_aclk,
+ M_AXI_GP0_ARREADY => '0',
+ M_AXI_GP0_AWREADY => '0',
+ M_AXI_GP0_BID => (others => '0'),
+ M_AXI_GP0_BRESP => (others =>'0'),
+ M_AXI_GP0_BVALID => '0',
+ M_AXI_GP0_RDATA => (others =>'0'),
+ M_AXI_GP0_RID => (others => '0'),
+ M_AXI_GP0_RLAST => '1',
+ M_AXI_GP0_RRESP => (others =>'0'),
+ M_AXI_GP0_RVALID => '0',
+ M_AXI_GP0_WREADY => '0',
+
+
+ S_AXI_HP0_ACLK => hp0_aclk,
+ S_AXI_HP0_ARADDR => hp0_araddr,
+ S_AXI_HP0_ARBURST => "01",
+ S_AXI_HP0_ARCACHE => "0001",
+ S_AXI_HP0_ARID => (others =>'0'),
+ S_AXI_HP0_ARLEN => "0000",
+ S_AXI_HP0_ARLOCK => "00",
+ S_AXI_HP0_ARPROT => "000",
+ S_AXI_HP0_ARQOS => "0000", -- not present in AXI3 which is this
+ S_AXI_HP0_ARREADY => hp0_arready,
+ S_AXI_HP0_ARSIZE =>"011", -- 8 bytes ??
+ S_AXI_HP0_ARVALID =>hp0_arvalid,
+ S_AXI_HP0_AWADDR => hp0_awaddr,
+ S_AXI_HP0_AWBURST => "01",
+ S_AXI_HP0_AWCACHE =>"0001",
+ S_AXI_HP0_AWID => (others =>'0'),
+ S_AXI_HP0_AWLEN => "0000",
+ S_AXI_HP0_AWLOCK => "00",
+ S_AXI_HP0_AWPROT =>"000",
+ S_AXI_HP0_AWQOS => "0000", -- not present in AXI3 which this is
+ S_AXI_HP0_AWREADY => hp0_awready,
+ S_AXI_HP0_AWSIZE =>"011", -- 8 bytes?
+ S_AXI_HP0_AWVALID => hp0_awvalid,
+ S_AXI_HP0_BID =>open,
+ S_AXI_HP0_BREADY => hp0_bready,
+ S_AXI_HP0_BRESP => open,
+ S_AXI_HP0_BVALID => hp0_bvalid,
+ S_AXI_HP0_RDATA => hp0_rdata,
+ S_AXI_HP0_RID => open,
+ S_AXI_HP0_RLAST =>open,
+ S_AXI_HP0_RREADY => hp0_rready,
+ S_AXI_HP0_RRESP => open,
+ S_AXI_HP0_RVALID => hp0_rvalid,
+ S_AXI_HP0_WDATA => hp0_wdata,
+ S_AXI_HP0_WID => "000000",
+ S_AXI_HP0_WLAST =>'1',
+ S_AXI_HP0_WREADY =>hp0_wready,
+ S_AXI_HP0_WSTRB => hp0_wstrb,
+ S_AXI_HP0_WVALID =>hp0_wvalid
+ );
+
+ eth0_mdio_mdio_iobuf: IOBUF
+ port map (
+ I => eth0_mdio_mdio_o,
+ IO => eth0_mdio_mdio_io,
+ O => eth0_mdio_mdio_i,
+ T => eth0_mdio_mdio_t
+ );
+
+
+ fifo_to_axi_i : entity work.fifo_to_axi
+ port map(
+ aclk => hp0_aclk,
+ aresetn => hp0_nrst,
+ axi_awaddr => hp0_awaddr,
+ axi_awvalid => hp0_awvalid,
+ axi_awready => hp0_awready,
+ axi_wdata => hp0_wdata,
+ axi_wstrb => hp0_wstrb,
+ axi_wvalid => hp0_wvalid,
+ axi_wready => hp0_wready,
+ axi_bvalid => hp0_bvalid,
+ axi_bready => hp0_bready,
+
+ pointer => fifo_pointer,
+ run => run,
+
+ fifo_empty =>dowrite,
+ fifo_rdata=> fifo_data,
+ fifo_rd_en => open
+ );
+
+
+ hp0_araddr<=(others=>'0');
+ hp0_arvalid <='0';
+ hp0_rready <='0';
+
+ fifo_data <= fifo_pointer & fifo_pointer;
+
+ process (hp0_aclk) begin
+ if rising_edge(hp0_aclk) then
+ if tc < 4 then
+ tc <= tc + 1;
+ dowrite <= '0';
+ else
+ tc <= 0;
+ dowrite <='1';
+ end if;
+ end if;
+ end process;
+
+
+ -----------------------------------------------------------------------------
+ -- IOs
+ -----------------------------------------------------------------------------
+
+ eth0_gmii_txd_o <= eth0_gmii_txd(eth0_gmii_txd_o'range);
+ eth0_gmii_rxd <= b"0000" & eth0_gmii_rxd_i;
+
+ red_led <= emio_o(0);
+ green_led <= emio_o(1);
+ run <= emio_o(2);
+
+
+end architecture arch;
generated by cgit v1.2.3 (git 2.25.1) at 2025-09-08 02:45:02 +0000