1 files changed, 138 insertions, 0 deletions
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
new file mode 100644
index 0000000..903334c
--- /dev/null
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -0,0 +1,138 @@
+# "Normal" constraints file- not early not late
+
+set_property PACKAGE_PIN U18 [get_ports {eth0_clk_o}]
+
+set_property PACKAGE_PIN U15 [get_ports {eth0_gmii_tx_clk_i}]
+set_property PACKAGE_PIN W19 [get_ports {eth0_gmii_tx_en_o[0]}]
+set_property PACKAGE_PIN W18 [get_ports {eth0_gmii_txd_o[0]}]
+set_property PACKAGE_PIN Y18 [get_ports {eth0_gmii_txd_o[1]}]
+set_property PACKAGE_PIN V18 [get_ports {eth0_gmii_txd_o[2]}]
+set_property PACKAGE_PIN Y19 [get_ports {eth0_gmii_txd_o[3]}]
+
+set_property PACKAGE_PIN U14 [get_ports {eth0_gmii_rx_clk_i}]
+set_property PACKAGE_PIN W16 [get_ports {eth0_gmii_rx_dv_i}]
+set_property PACKAGE_PIN Y16 [get_ports {eth0_gmii_rxd_i[0]}]
+set_property PACKAGE_PIN V16 [get_ports {eth0_gmii_rxd_i[1]}]
+set_property PACKAGE_PIN V17 [get_ports {eth0_gmii_rxd_i[2]}]
+set_property PACKAGE_PIN Y17 [get_ports {eth0_gmii_rxd_i[3]}]
+
+
+set_property PACKAGE_PIN W15 [get_ports {eth0_mdio_mdc_o}]
+set_property PACKAGE_PIN Y14 [get_ports {eth0_mdio_mdio_io}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports eth0_*]
+
+set_property PACKAGE_PIN W13 [get_ports {green_led}]
+set_property PACKAGE_PIN W14 [get_ports {red_led}]
+
+set_property IOSTANDARD LVCMOS33 [get_ports *_led]
+
+
+#set_property IOSTANDARD LVCMOS33 [get_ports clk_50m]
+#set_property PACKAGE_PIN R4 [get_ports clk_50m]
+
+#set_property PACKAGE_PIN T1 [get_ports {led_1}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
+
+#set_property PACKAGE_PIN U3 [get_ports {hdmi_r_p}]
+#set_property PACKAGE_PIN V3 [get_ports {hdmi_r_n}]
+#set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}]
+#set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}]
+#set_property PACKAGE_PIN R3 [get_ports {hdmi_b_p}]
+#set_property PACKAGE_PIN R2 [get_ports {hdmi_b_n}]
+#set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}]
+#set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}]
+#
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_c_n}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_r_n}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_g_n}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_p}]
+#set_property IOSTANDARD TMDS_33 [get_ports {hdmi_b_n}]
+#
+##set_property DRIVE 16 [get_ports {hdmi_c_p}]
+##set_property DRIVE 16 [get_ports {hdmi_c_n}]
+##set_property DRIVE 16 [get_ports {hdmi_r_p}]
+##set_property DRIVE 16 [get_ports {hdmi_r_n}]
+##set_property DRIVE 16 [get_ports {hdmi_g_p}]
+##set_property DRIVE 16 [get_ports {hdmi_g_n}]
+##set_property DRIVE 16 [get_ports {hdmi_b_p}]
+#
+#set_property PACKAGE_PIN W1 [get_ports {hdmi_vcc}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_vcc}]
+#
+# 
+##set_property PACKAGE_PIN P20 [get_ports rxd]
+##set_property PACKAGE_PIN T20 [get_ports txd]
+##set_property IOSTANDARD LVCMOS33 [get_ports rxd]
+##set_property IOSTANDARD LVCMOS33 [get_ports txd]
+#
+##set_property PACKAGE_PIN T3 [get_ports key]
+##set_property IOSTANDARD LVCMOS33 [get_ports key]
+#
+#set_property PACKAGE_PIN N22 [get_ports {video[0]}]
+#set_property PACKAGE_PIN N20 [get_ports {video[1]}]
+#set_property PACKAGE_PIN N18 [get_ports {video[2]}]
+#set_property PACKAGE_PIN K18 [get_ports {video[3]}]
+#set_property PACKAGE_PIN M18 [get_ports {video[4]}]
+#set_property PACKAGE_PIN M15 [get_ports {video[5]}]
+#set_property PACKAGE_PIN U20 [get_ports {video[6]}]
+#set_property PACKAGE_PIN T21 [get_ports {video[7]}]
+#
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
+#
+#set_property PACKAGE_PIN W19 [get_ports {pclk_in}]
+#set_property PACKAGE_PIN R18 [get_ports {vsync_in}]
+#set_property PACKAGE_PIN Y18 [get_ports {hsync_in}]
+#set_property PACKAGE_PIN P16 [get_ports {r_out}]
+#set_property PACKAGE_PIN V18 [get_ports {g_out}]
+#set_property PACKAGE_PIN P15 [get_ports {b_out}]
+#set_property PACKAGE_PIN P14 [get_ports {i_clk_out}]
+#set_property PACKAGE_PIN V17 [get_ports {hsync_out}]
+#set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
+#
+#
+#set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {vsync_in}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {r_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {g_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {b_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {i_clk_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {hsync_out}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {vsync_out}]
+#
+#set_property PACKAGE_PIN AA18 [get_ports {sys_rst_n}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {sys_rst_n}]
+#set_property PULLTYPE PULLUP [get_ports {sys_rst_n}]
+#		
+#create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m]
+##set_false_path -from [get_ports pci_exp_rst_n]
+
+
+###############################################################################
+# Additional design / project settings
+###############################################################################
+
+# Power down on overtemp
+set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
+set_property BITSTREAM.CONFIG.USERID 32'hf00dbabe [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+
+
+
+