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-rw-r--r--fpga/hp_lcd_driver/common.vhdl20
1 files changed, 10 insertions, 10 deletions
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl
index df58203..7275184 100644
--- a/fpga/hp_lcd_driver/common.vhdl
+++ b/fpga/hp_lcd_driver/common.vhdl
@@ -84,8 +84,8 @@ architecture Behavioral of common is
signal c : natural;
signal t : std_logic;
-
- signal wr_index: std_logic;
+
+ signal wr_index : std_logic;
begin
@@ -250,19 +250,19 @@ begin
- r <=x"ff" when rd_data(0) = '1' else
- x"00";
+ r <= x"ff" when rd_data(0) = '1' else
+ x"00";
-- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
-- x"80" when rd_data(0)='1' else
-- x"00";
- g <=x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else
- x"80" when rd_data(1) = '1' else
- x"00";
- b <=x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else
- x"80" when rd_data(2) = '1' else
- x"00";
+ g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else
+ x"80" when rd_data(1) = '1' else
+ x"00";
+ b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else
+ x"80" when rd_data(2) = '1' else
+ x"00";