diff options
| -rw-r--r-- | fpga/hp_lcd_driver/common.vhdl | 20 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/fifo_to_axi.vhdl | 8 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/hp_lcd_driver.vhdl | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/tmds_phy_artix7.vhdl | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/vnc_serializer.vhdl | 26 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_wrapper.vhdl | 85 |
6 files changed, 72 insertions, 71 deletions
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl index df58203..7275184 100644 --- a/fpga/hp_lcd_driver/common.vhdl +++ b/fpga/hp_lcd_driver/common.vhdl @@ -84,8 +84,8 @@ architecture Behavioral of common is signal c : natural; signal t : std_logic; - - signal wr_index: std_logic; + + signal wr_index : std_logic; begin @@ -250,19 +250,19 @@ begin - r <=x"ff" when rd_data(0) = '1' else - x"00"; + r <= x"ff" when rd_data(0) = '1' else + x"00"; -- r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else -- x"80" when rd_data(0)='1' else -- x"00"; - g <=x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else - x"80" when rd_data(1) = '1' else - x"00"; - b <=x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else - x"80" when rd_data(2) = '1' else - x"00"; + g <= x"ff" when rd_data(1) = '1' and rd_data(3) = '1' else + x"80" when rd_data(1) = '1' else + x"00"; + b <= x"ff" when rd_data(2) = '1' and rd_data(3) = '1' else + x"80" when rd_data(2) = '1' else + x"00"; diff --git a/fpga/hp_lcd_driver/fifo_to_axi.vhdl b/fpga/hp_lcd_driver/fifo_to_axi.vhdl index 64da115..c527ea1 100644 --- a/fpga/hp_lcd_driver/fifo_to_axi.vhdl +++ b/fpga/hp_lcd_driver/fifo_to_axi.vhdl @@ -87,10 +87,10 @@ begin elsif do_bus_cycle = '0' then if fifo_empty = '0' then - data <= fifo_rdata (63 downto 0); - if fifo_rdata(64)='1' then - addr <= std_logic_vector(START); - end if; + data <= fifo_rdata (63 downto 0); + if fifo_rdata(64) = '1' then + addr <= std_logic_vector(START); + end if; fifo_rd_en <= '1'; do_bus_cycle <= '1'; axi_awvalid <= '1'; diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl index 491ccf3..15fe76f 100644 --- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl @@ -71,7 +71,7 @@ begin hdmi_vcc => hdmi_vcc, i_clk_out => i_clk_out, led => led, - video_out_clk => open, + video_out_clk => open, video_out_index => open, video_out_data => open, video_out_valid => open diff --git a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl index 8c8106e..722467b 100644 --- a/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl +++ b/fpga/hp_lcd_driver/tmds_phy_artix7.vhdl @@ -73,7 +73,7 @@ begin sr <= ld; else sr(8 downto 0) <= sr (9 downto 1); - s <=sr(0); + s <= sr(0); end if; end if; end process; diff --git a/fpga/hp_lcd_driver/vnc_serializer.vhdl b/fpga/hp_lcd_driver/vnc_serializer.vhdl index ce4b951..855c2d7 100644 --- a/fpga/hp_lcd_driver/vnc_serializer.vhdl +++ b/fpga/hp_lcd_driver/vnc_serializer.vhdl @@ -24,7 +24,7 @@ architecture Behavioural of vnc_serializer is signal i : natural := 0; signal wren : std_logic; signal next_index : std_logic; - signal index : std_logic; + signal index : std_logic; begin process (clk) @@ -34,22 +34,22 @@ begin if vnc_index = '1' then reg(0) <= vnc_data; next_index <= '1'; - i <=1; - wren <= '0'; + i <= 1; + wren <= '0'; else reg(i) <= vnc_data; if i /= 7 then - i <=i+1; + i <= i+1; wren <= '0'; else - i <=0; - wren <= '1'; - index <= next_index; - next_index <= '0'; + i <= 0; + wren <= '1'; + index <= next_index; + next_index <= '0'; end if; - end if; + end if; else - wren <= '0'; + wren <= '0'; end if; end if; end process; @@ -57,11 +57,11 @@ begin g_j : for j in 0 to 7 generate - fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j); - fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others =>'0'); + fifo_data(((j*8)+video_width-1) downto (j*8)) <= reg(j); + fifo_data(((j*8)+7) downto ((j*8)+video_width)) <= (others => '0'); end generate g_j; - fifo_data(64)<=index; + fifo_data(64) <= index; fifo_wren <= wren; diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl index 1fde3c8..529a1b1 100644 --- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl +++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl @@ -129,12 +129,12 @@ architecture arch of zynq7_wrapper is signal fifo_rst_cnt : natural; - signal fifo_rst: std_logic; - signal fifo_wr_en : std_logic; - signal fifo_wdata : std_logic_vector(64 downto 0); - signal fifo_rd_en : std_logic; - signal fifo_rdata : std_logic_vector(64 downto 0); - signal fifo_empty : std_logic; + signal fifo_rst : std_logic; + signal fifo_wr_en : std_logic; + signal fifo_wdata : std_logic_vector(64 downto 0); + signal fifo_rd_en : std_logic; + signal fifo_rdata : std_logic_vector(64 downto 0); + signal fifo_empty : std_logic; signal run : std_logic; @@ -309,43 +309,44 @@ begin vnc_serializer_i : entity work.vnc_serializer - generic map ( - video_width => video_width - ) - port map ( - clk => vnc_clk, - vnc_valid => vnc_valid, - vnc_data => vnc_data, - vnc_index => vnc_index, - - fifo_data => fifo_wdata, - fifo_wren => fifo_wr_en); - - -process (clk_50m) begin -if rising_edge(clk_50m) then -if sys_rst_n='0' then - fifo_rst_cnt <= 20; - fifo_rst <='1'; -elsif fifo_rst_cnt /= 0 then - fifo_rst_cnt <= fifo_rst_cnt -1; -else - fifo_rst <='0'; -end if; -end if; -end process; + generic map ( + video_width => video_width + ) + port map ( + clk => vnc_clk, + vnc_valid => vnc_valid, + vnc_data => vnc_data, + vnc_index => vnc_index, + + fifo_data => fifo_wdata, + fifo_wren => fifo_wr_en); + + + process (clk_50m) + begin + if rising_edge(clk_50m) then + if sys_rst_n = '0' then + fifo_rst_cnt <= 20; + fifo_rst <= '1'; + elsif fifo_rst_cnt /= 0 then + fifo_rst_cnt <= fifo_rst_cnt -1; + else + fifo_rst <= '0'; + end if; + end if; + end process; fifo_i : entity work.fifo_generator_0 - port map ( - rst => fifo_rst, - wr_clk => vnc_clk, - din => fifo_wdata, - wr_en => fifo_wr_en, - rd_clk=>hp0_aclk, - rd_en =>fifo_rd_en, - dout => fifo_rdata, - empty => fifo_empty - ); + port map ( + rst => fifo_rst, + wr_clk => vnc_clk, + din => fifo_wdata, + wr_en => fifo_wr_en, + rd_clk => hp0_aclk, + rd_en => fifo_rd_en, + dout => fifo_rdata, + empty => fifo_empty + ); @@ -363,7 +364,7 @@ end process; axi_bvalid => hp0_bvalid, axi_bready => hp0_bready, - run => run, + run => run, fifo_empty => fifo_empty, fifo_rdata => fifo_rdata, |