tidy

13 files changed, 0 insertions, 1076 deletions

diff --git a/smh-ac415-fpga/lcd_driver/.gitignore b/smh-ac415-fpga/lcd_driver/.gitignore
deleted file mode 100644
index da1292e..0000000
--- a/smh-ac415-fpga/lcd_driver/.gitignore
+++ /dev/null
@@ -1,6 +0,0 @@
-*.svf
-*.qws
-db
-incremental_db
-greybox_tmp
-output_files
diff --git a/smh-ac415-fpga/lcd_driver/Makefile b/smh-ac415-fpga/lcd_driver/Makefile
deleted file mode 100644
index 530157e..0000000
--- a/smh-ac415-fpga/lcd_driver/Makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-PROJECT = lcd_driver
-SOURCE_FILES = a_input.vhdl a_siggen.vhdl clk1.vhdl clk2.vhdl ddio_out.vhdl debounce.vhdl edge_det.vhdl hdmi_driver.vhdl lcd_driver.vhdl synchronizer.vhdl video_ram.vhdl
-ASSIGNMENT_FILES = lcd_driver.qpf lcd_driver.qsf 
-
-BUILD=output_files
-
-OPENOCD=openocd -f interface/altera-usb-blaster.cfg -f cpld/altera-epm240.cfg
-
-MAP_ARGS = --smart 
-FIT_ARGS = 
-ASM_ARGS =
-STA_ARGS =
-CPF_ARGS = -c -q 1MHZ -g 3.3 -n p
-
-SVF=${PROJECT}.svf
-
-
-default: ${SVF}
-
-${SVF}: ${BUILD}/${PROJECT}.svf
-	cat $< > $@ || /bin/rm -f $@
-
-program: ${SVF}
-	${OPENOCD} -c "init; svf $<; exit"
-
-all: ${BUILD}/$(PROJECT).asm.rpt ${BUILD}/$(PROJECT).sta.rpt  ${BUILD}/${PROJECT}.svf
-
-clean:
-	rm -rf db ${BUILD} *.orig *.bak incremental_db
-
-map: ${BUILD}/$(PROJECT).map.rpt
-fit: ${BUILD}/$(PROJECT).fit.rpt
-asm: ${BUILD}/$(PROJECT).asm.rpt
-sta: ${BUILD}/$(PROJECT).sta.rpt
-
-${BUILD}/$(PROJECT).map.rpt: $(SOURCE_FILES) 
-	run_quartus quartus_map $(MAP_ARGS) ${PROJECT} 
-
-${BUILD}/$(PROJECT).fit.rpt: ${BUILD}/$(PROJECT).map.rpt
-	run_quartus quartus_fit $(FIT_ARGS) $(PROJECT)
-
-${BUILD}/$(PROJECT).asm.rpt: ${BUILD}/$(PROJECT).fit.rpt
-	run_quartus quartus_asm $(ASM_ARGS) $(PROJECT)
-
-${BUILD}/$(PROJECT).sta.rpt: ${BUILD}/$(PROJECT).fit.rpt
-	run_quartus quartus_sta $(STA_ARGS) $(PROJECT) 
-
-${BUILD}/$(PROJECT).sof: ${BUILD}/$(PROJECT).asm.rpt
-
-${BUILD}/$(PROJECT).svf:  ${BUILD}/$(PROJECT).sof
-	run_quartus quartus_cpf  ${CPF_ARGS} $< $@
-
-tidy:
-	for i in ${SOURCE_FILES}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
-
-
diff --git a/smh-ac415-fpga/lcd_driver/a_input.vhdl b/smh-ac415-fpga/lcd_driver/a_input.vhdl
deleted file mode 100644
index 434d820..0000000
--- a/smh-ac415-fpga/lcd_driver/a_input.vhdl
+++ /dev/null
@@ -1,174 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY a_input IS
-    generic (debounce_stages : natural := 2;
-             sync_stages     : natural := 2;
-	     hres	     : natural := 594;
-             front_porch     : natural := 100;
-	     p_clk_multiple  : natural := 4;
-	     vres            : natural := 384);
-
-	PORT
-	(
-	  p_clk : in std_logic;
-	  sys_rst_n : in std_logic;
-	  video_in:in std_logic;
-	  bright_in:in std_logic;
-	  hsync_in:in std_logic;
-	  vsync_in: in std_logic;
-	  video_out: out std_logic_vector(1 downto 0);
-	  addr_out : out std_logic_vector(17 downto 0);
-	  wren_out : out std_logic;
-	  p_clk_out : out std_logic
-	  );
-	  
-END a_input;
-
-
-ARCHITECTURE beh OF a_input IS
-
-   signal p_clk_div : natural;
-   signal row_addr : std_logic_vector(17 downto 0)	;
-   signal addr : std_logic_vector(17 downto 0)	;
-   signal wren: std_logic;
-
-
- signal s_hsync: std_logic;
- signal d_hsync: std_logic;
- signal pe_hsync: std_logic;
- signal ne_hsync: std_logic;
-
-
- signal s_vsync: std_logic;
- signal d_vsync: std_logic;
-
- signal s_video: std_logic;
- signal s_bright: std_logic;
-
- signal fp_counter:natural;
- signal active_counter:natural;
-
-		
-begin
-
-	
-
-    video_sync: entity work.synchronizer
-		generic map(stages => sync_stages +debounce_stages)
-		port map (
-			clk=>p_clk,
-			i => video_in,
-			o =>s_video
-			);
-
-
-
-    bright_sync: entity work.synchronizer
-		generic map(stages => sync_stages +debounce_stages)
-		port map (
-			clk=>p_clk,
-			i => bright_in,
-			o =>s_bright
-			);
-
-
-    hsync_sync: entity work.synchronizer
-		generic map(stages => sync_stages)
-		port map (
-			clk=>p_clk,
-			i => hsync_in,
-			o =>s_hsync
-			);
-
-
-
-    vsync_sync: entity work.synchronizer
-		generic map(stages => sync_stages  )
-		port map (
-			clk=>p_clk,
-			i => vsync_in,
-			o =>s_vsync
-			);
-
-    hsync_debounce : entity work.debounce
-        generic map(stages => debounce_stages)
-        port map(
-            clk => p_clk,
-            i   => s_hsync,
-            o   => d_hsync);
-
-
-    hsync_ed : entity work.edge_det
-        port map(
-            clk => p_clk,
-            sig => d_hsync,
-            pe  => pe_hsync,
-            ne  => ne_hsync);
-
-
-
-
-    vsync_debounce : entity work.debounce
-        generic map(stages => debounce_stages)
-        port map(
-            clk => p_clk,
-            i   => s_vsync,
-            o   => d_vsync);
-
-
-
--- horizontal state machine
-
-	process (sys_rst_n,p_clk,d_hsync,d_vsync)  begin
-	if sys_rst_n = '0' then
-		row_addr<=(others =>'0');
-		addr<=(others =>'0');
-		p_clk_div<=p_clk_multiple;
-		active_counter <=0;
-		fp_counter <=0;
-	elsif rising_edge(p_clk) then
-		if d_vsync='1' then
-			row_addr<=(others => '0');
-			addr<=(others => '0');
-			fp_counter <= front_porch;
-			active_counter <=hres;
-			p_clk_div <=p_clk_multiple;
-            	elsif pe_gsync ='1' then
-			row_addr <= std_logic_vector(unsigned(row_addr)+1);
-		elsif ne_hsync='1' then
-			fp_counter <= front_porch;
-			active_counter <=hres;
-			p_clk_div <=p_clk_multiple;
-			addr<=row_addr;
-		elsif fp_counter /= 0 then
-			fp_counter <= fp_counter -1;
-		elsif active_counter /= 0 then	
-			if p_clk_div = 0 then
-				p_clk_div <=p_clk_multiple;
-				active_counter <= active_counter  -1;
-		   		addr <= std_logic_vector(unsigned(addr)+vres);
-			else 
-				p_clk_div <= p_clk_div - 1;
-			end if;
-		else 
-			p_clk_div <=p_clk_multiple;
-		end if;
-	end if;
-	end process;
-			
-
-        wren <= '1' when p_clk_div=2 else '0';
-
-	addr_out <= addr;
-        video_out <= (s_video, s_bright);
-        wren_out <= wren;
-
-        p_clk_out <= p_clk;
-
-
-end beh;
diff --git a/smh-ac415-fpga/lcd_driver/ddio_out.vhdl b/smh-ac415-fpga/lcd_driver/ddio_out.vhdl
deleted file mode 100644
index 9c634f4..0000000
--- a/smh-ac415-fpga/lcd_driver/ddio_out.vhdl
+++ /dev/null
@@ -1,111 +0,0 @@
--- megafunction wizard: %ALTDDIO_OUT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: ALTDDIO_OUT 
-
--- ============================================================
--- File Name: ddio_out.vhd
--- Megafunction Name(s):
--- 			ALTDDIO_OUT
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY ddio_out IS
-	PORT
-	(
-		datain_h		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		datain_l		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
-		outclock		: IN STD_LOGIC ;
-		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
-	);
-END ddio_out;
-
-
-ARCHITECTURE SYN OF ddio_out IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
-
-BEGIN
-	dataout    <= sub_wire0(0 DOWNTO 0);
-
-	ALTDDIO_OUT_component : ALTDDIO_OUT
-	GENERIC MAP (
-		extend_oe_disable => "OFF",
-		intended_device_family => "Cyclone IV E",
-		invert_output => "OFF",
-		lpm_hint => "UNUSED",
-		lpm_type => "altddio_out",
-		oe_reg => "UNREGISTERED",
-		power_up_high => "OFF",
-		width => 1
-	)
-	PORT MAP (
-		datain_h => datain_h,
-		datain_l => datain_l,
-		outclock => outclock,
-		dataout => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: CONSTANT: EXTEND_OE_DISABLE STRING "OFF"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: CONSTANT: INVERT_OUTPUT STRING "OFF"
--- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altddio_out"
--- Retrieval info: CONSTANT: OE_REG STRING "UNREGISTERED"
--- Retrieval info: CONSTANT: POWER_UP_HIGH STRING "OFF"
--- Retrieval info: CONSTANT: WIDTH NUMERIC "1"
--- Retrieval info: USED_PORT: datain_h 0 0 1 0 INPUT NODEFVAL "datain_h[0..0]"
--- Retrieval info: CONNECT: @datain_h 0 0 1 0 datain_h 0 0 1 0
--- Retrieval info: USED_PORT: datain_l 0 0 1 0 INPUT NODEFVAL "datain_l[0..0]"
--- Retrieval info: CONNECT: @datain_l 0 0 1 0 datain_l 0 0 1 0
--- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
--- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
--- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT_CLK_EXT NODEFVAL "outclock"
--- Retrieval info: CONNECT: @outclock 0 0 0 0 outclock 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.vhd TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.qip TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.bsf TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out_inst.vhd TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.inc TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.cmp TRUE TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL ddio_out.ppf TRUE FALSE
--- Retrieval info: LIB_FILE: altera_mf
-
diff --git a/smh-ac415-fpga/lcd_driver/debounce.vhdl b/smh-ac415-fpga/lcd_driver/debounce.vhdl
deleted file mode 100644
index 654a2f3..0000000
--- a/smh-ac415-fpga/lcd_driver/debounce.vhdl
+++ /dev/null
@@ -1,32 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity debounce is
-    generic (stages : natural := 1);
-    port (clk : in  std_logic;
-          i   : in  std_logic;
-          o   : out std_logic);
-end debounce;
-
-architecture Behavioral of debounce is
-    signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
-    constant zero    : std_logic_vector(stages-1 downto 0) := (others => '0');
-    constant one     : std_logic_vector(stages-1 downto 0) := (others => '1');
-    signal output    : std_logic                           := '0';
-begin
-
-    o <= output;
-
-    process (clk,flipflops,i)
-    begin
-        if rising_edge(clk) then
-            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
-            if flipflops = one and i = '1' then
-                output <= '1';
-            elsif flipflops = zero and i = '0' then
-                output <= '0';
-            end if;
-        end if;
-    end process;
-
-end architecture;
diff --git a/smh-ac415-fpga/lcd_driver/edge_det.vhdl b/smh-ac415-fpga/lcd_driver/edge_det.vhdl
deleted file mode 100644
index 8cb38eb..0000000
--- a/smh-ac415-fpga/lcd_driver/edge_det.vhdl
+++ /dev/null
@@ -1,28 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity edge_det is
-    port (clk : in  std_logic;
-          sig : in  std_logic;
-          pe  : out std_logic;
-          ne  : out std_logic;
-          e   : out std_logic
-          );
-end edge_det;
-
-architecture Behavioral of edge_det is
-    signal last : std_logic := '0';
-begin
-
-    process(clk,last,sig) 
-    begin
-        if rising_edge(clk) then
-            last <= sig;
-        end if;
-    end process;
-
-    pe <= '1' when sig = '1' and last = '0' else '0';
-    ne <= '1' when sig = '0' and last = '1' else '0';
-
-    e <= sig xor last;
-end Behavioral;
diff --git a/smh-ac415-fpga/lcd_driver/hdmi_driver.vhdl b/smh-ac415-fpga/lcd_driver/hdmi_driver.vhdl
deleted file mode 100644
index 7c6b422..0000000
--- a/smh-ac415-fpga/lcd_driver/hdmi_driver.vhdl
+++ /dev/null
@@ -1,52 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.altera_mf_components.all;
-
-ENTITY hdmi_driver IS
-	PORT
-	(
-		in_h		: in std_logic;
-		in_l		: in std_logic;
-		clk	   	: in std_logic;
-		output		: out std_logic
-	);
-END hdmi_driver;
-
-
-ARCHITECTURE beh OF hdmi_driver IS
-
-   signal out_v   : std_logic_vector(0 downto 0);
-	signal out_n_v   : std_logic_vector(0 downto 0);
-	signal in_l_v   : std_logic_vector(0 downto 0);
-	signal in_h_v   : std_logic_vector(0 downto 0);
-	
-BEGIN
-	
-	output <= out_v(0);
-	in_l_v(0) <= in_l;
-	in_h_v(0) <= in_h;
-	
-	ddio_p : ALTDDIO_OUT
-	GENERIC MAP (
-		extend_oe_disable => "OFF",
-		intended_device_family => "Cyclone IV E",
-		invert_output => "OFF",
-		lpm_hint => "UNUSED",
-		lpm_type => "altddio_out",
-		oe_reg => "UNREGISTERED",
-		power_up_high => "OFF",
-		width => 1
-	)
-	PORT MAP (
-		datain_h => in_h_v,
-		datain_l => in_l_v,
-		outclock => clk,
-		dataout => out_v
-	);
-
-
-END beh;
-
-
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.qpf b/smh-ac415-fpga/lcd_driver/lcd_driver.qpf
deleted file mode 100644
index fbfca6e..0000000
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.qpf
+++ /dev/null
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 11:47:00  April 20, 2025
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "13.0"
-DATE = "11:47:00  April 20, 2025"
-
-# Revisions
-
-PROJECT_REVISION = "lcd_driver"
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.qsf b/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
deleted file mode 100644
index 7607808..0000000
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.qsf
+++ /dev/null
@@ -1,100 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2013 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 32-bit
-# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
-# Date created = 11:47:00  April 20, 2025
-#
-# -------------------------------------------------------------------------- #
-#
-# Notes:
-#
-# 1) The default values for assignments are stored in the file:
-#		lcd_driver_assignment_defaults.qdf
-#    If this file doesn't exist, see file:
-#		assignment_defaults.qdf
-#
-# 2) Altera recommends that you do not modify this file. This
-#    file is updated automatically by the Quartus II software
-#    and any changes you make may be lost or overwritten.
-#
-# -------------------------------------------------------------------------- #
-
-
-set_global_assignment -name FAMILY "Cyclone IV E"
-set_global_assignment -name DEVICE EP4CE15F23C8
-set_global_assignment -name TOP_LEVEL_ENTITY lcd_driver
-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:47:00  APRIL 20, 2025"
-set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
-set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
-
-
-set_location_assignment PIN_T22 -to clk_50m
-set_location_assignment PIN_U20 -to sys_rst_n
-
-
-set_location_assignment PIN_H22 -to hdmi_clk_n
-set_location_assignment PIN_H21 -to hdmi_clk_p
-
-#set_location_assignment PIN_F22 -to hdmi_red_n
-#set_location_assignment PIN_E22 -to hdmi_green_n
-#set_location_assignment PIN_D22 -to hdmi_blue_n
-
-set_location_assignment PIN_F21 -to hdmi_red
-set_location_assignment PIN_E21 -to hdmi_green
-set_location_assignment PIN_D21 -to hdmi_blue
-
-
-set_location_assignment PIN_N22 -to hdmi_ddc_scl
-set_location_assignment PIN_R22 -to hdmi_ddc_sda
-
-
-
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_clk
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_red
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_green
-set_instance_assignment -name IO_STANDARD LVDS -to hdmi_blue
-
-
-
-
-set_global_assignment -name VHDL_FILE clk1.vhdl
-set_global_assignment -name VHDL_FILE clk2.vhdl
-set_global_assignment -name VHDL_FILE edge_det.vhdl
-set_global_assignment -name VHDL_FILE debounce.vhdl
-set_global_assignment -name VHDL_FILE synchronizer.vhdl
-set_global_assignment -name VHDL_FILE video_ram.vhdl
-set_global_assignment -name VHDL_FILE lcd_driver.vhdl
-set_global_assignment -name VHDL_FILE hdmi_driver.vhdl
-set_global_assignment -name VHDL_FILE a_input.vhdl
-set_global_assignment -name VHDL_FILE a_siggen.vhdl
-
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
deleted file mode 100644
index 8a07fde..0000000
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
+++ /dev/null
@@ -1,169 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity lcd_driver is
-     port (
-        clk_50m : in std_logic;
-        sys_rst_n : in  std_logic;
-		
-		s_video : in std_logic;
-		s_bright : in std_logic;
-		s_hsync : in std_logic;
-		s_vsync : in std_logic;
-		
-		hdmi_ddc_scl : inout std_logic;
-		hdmi_ddc_sda : inout std_logic;
-
-		hdmi_clk : out std_logic;
-		hdmi_red : out std_logic;
-		hdmi_green : out std_logic;
-		hdmi_blue : out std_logic
-
-
-
---		hdmi_clk_p : out std_logic;
---		hdmi_clk_n : out std_logic;
---		hdmi_red_p : out std_logic;
---		hdmi_red_n : out std_logic;
---		hdmi_green_p : out std_logic;
---		hdmi_green_n : out std_logic;
---		hdmi_blue_p : out std_logic;
---		hdmi_blue_n : out std_logic
- );
-end entity lcd_driver;
-
-architecture behavioural of lcd_driver is
-
-	
-		signal wren :std_logic;
-	        signal w_addr :std_logic_vector(17 downto 0);
-		signal r_addr :std_logic_vector(17 downto 0);
-		
-		signal clk_80m : std_logic;
-		signal clk_20m : std_logic;
-		signal clk_91_25m : std_logic;
-	
-		signal a_bright: std_logic;
-		signal a_video: std_logic;
-		signal a_hsync: std_logic;
-		signal a_vsync : std_logic;
-
-
-		signal a_data : std_logic_vector(1 downto 0);
-
-		signal f_data : std_logic_vector(1 downto 0);
-
-		signal f_red : std_logic_vector(7 downto 0);
-		signal f_green : std_logic_vector(7 downto 0);
-		signal f_blue : std_logic_vector(7 downto 0);
-		signal f_hsync:  std_logic;
-		signal f_vsync : std_logic;
-
-		signal h_data : std_logic_vector(1 downto 0);
-	
-begin
-
-
--- gtf at 30Hz   xrandr --newmode "$M" 127.98  1536 1632 1792 2048  2048 2049 2052 2083  -HSync +Vsync
--- works at 60Hz xrandr --newmode "$M" 213.06  1536 1544 1552 1728  2048 2049 2051 2055  -HSync +Vsync
--- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
-
-
-     clk1_0:work.clk1
-	port map (
-		areset => not sys_rst_n,
-		inclk0 => clk_50m,
-		c0 => clk_80m,
-		c1 => clk_20m
-	);
-
-
-     clk2_0:work.clk2
-	port map (
-		areset => not sys_rst_n,
-		inclk0 => clk_50m,
-		c0 => clk_91_25m
-	);
-
-
-   
-	a_siggen0:work.a_siggen 
-	port map (
-	  sys_rst_n => sys_rst_n,
-		pclk => clk_20m,
-		bright=> a_bright,
-		video => a_video,
-		hsync => a_hsync,
-		vsync => a_vsync
-	);
-   
-
-
-	a_input0: work.a_input
-	port map (
-	  sys_rst_n => sys_rst_n,
-	  p_clk => clk_80m,
-	  
-	  video_in => a_video,
-	  bright_in => a_bright,
-	  hsync_in => a_hsync,
-	  vsync_in => a_vsync,
-	  
-	  video_out =>  a_data,
-	  addr_out  => w_addr,
-	  wren_out => wren
-	  );
-
-
-
-	formatter0: work.formatter
-	port map (
-	  sys_rst_n => sys_rst_n,
-	  p_clk => clk_91_25m,
-
-	  addr_out => r_addr,
-	  hsync_out => h_hsync,
-	  vsync_out => h_vsync,
-	  wren_out => wren
-	  );
-
-
-   
-	
-   process (sys_rst_n,r_addr,clk_91_25m)  begin 
-		if sys_rst_n = '0' then 
-			r_addr <=(others =>'0');
-		elsif rising_edge(clk_91_25m) then
-		   r_addr <= std_logic_vector(unsigned(w_addr)+1);
-		end if;
-	end process;
-	
-   vram: work.video_ram
-   PORT MAP (
-		data		=>a_data,
-		wraddress	=>w_addr,
-		wrclock		=>clk_80m,
-		wren		=> wren,
-		
-		rdaddress => r_addr,
-		rdclock	 => clk_91_25m,
-		q		=> h_data
-	);
-
-
-
-
-	
-
-	red_driver : work.hdmi_driver
-	PORT MAP (
-		in_h => h_data(0),
-		in_l => h_data(1),
-		clk => clk_91_25m,
-		output => hdmi_red
-	);
- 	
-	
-	
-end behavioural;
diff --git a/smh-ac415-fpga/lcd_driver/scripts/vhdl-pretty b/smh-ac415-fpga/lcd_driver/scripts/vhdl-pretty
deleted file mode 100755
index c514b85..0000000
--- a/smh-ac415-fpga/lcd_driver/scripts/vhdl-pretty
+++ /dev/null
@@ -1,60 +0,0 @@
-#! /bin/sh
-":"; exec emacs --no-site-file --script "$0" -- "$0" "$@" # -*-emacs-lisp-*-
-; vim: noai:ts=4:sw=4:syntax=lisp
-
-(setq arg0 (file-truename (car (cdr argv))))
-(setq args (cdr (cdr argv)))
-(setq argv nil)
-
-; Parse the command line arguments,
-;  --xxx           -> ("xxx" t)
-;  --no-xxx        -> ("xxx" nil)
-;  --xxx=123       -> ("xxx" 123)
-;  --xxx=abc       -> ("xxx" "abc")
-;  --xxx='abc 123' -> ("xxx" "abc 123")
-;  --xxx=abc=123   -> ("xxx" "abc=123")
-(setq args
-  (mapcar
-    (lambda (arg)
-      (cond
-        ((string-match "^--no-\\([^=]*\\)$" arg)
-          (list (intern (match-string 1 arg)) nil))
-        ((string-match "^--\\([^=]*\\)$" arg)
-          (list (intern (match-string 1 arg)) t))
-        ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\([0-9]+\\)\\2$" arg)
-          (list (intern (match-string 1 arg)) (string-to-number (match-string 3 arg))))
-        ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\(.+?\\)\\2$" arg)
-          (list (intern (match-string 1 arg)) (match-string 3 arg)))
-        (t nil)
-      ))
-    args))
-
-; Read stdin into buffer
-(defun insert-standard-input ()
-  "insert contents from standard input"
-  (condition-case nil
-      (let (line)
-        (while (setq line (read-from-minibuffer ""))
-          (insert line "\n")))
-    (error nil)))
-
-(insert-standard-input)
-(goto-char (point-min))
-
-; Load library
-(setq basedir (concat (file-name-directory arg0) "vhdl-mode"))
-(setq load-path (cons basedir load-path))
-(load-library "vhdl-mode")
-
-; Default customisation
-(vhdl-set-style "IEEE")
-
-; Customisation from cmdline
-(mapc (lambda (arg) (customize-set-variable (car arg) (car (cdr arg)))) args)
-
-; Turn on mode and beautify
-(vhdl-mode)
-(vhdl-beautify-region (point-min) (point-max))
-
-; Output buffer to stdout
-(princ (buffer-string))
diff --git a/smh-ac415-fpga/lcd_driver/synchronizer.vhdl b/smh-ac415-fpga/lcd_driver/synchronizer.vhdl
deleted file mode 100644
index 99618b9..0000000
--- a/smh-ac415-fpga/lcd_driver/synchronizer.vhdl
+++ /dev/null
@@ -1,26 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity synchronizer is
-    generic (stages : natural := 2);
-    port (clk : in  std_logic;
-          i   : in  std_logic;
-          o   : out std_logic);
-end synchronizer;
-
-architecture Behavioral of synchronizer is
-    signal flipflops                 : std_logic_vector(stages-1 downto 0) := (others => '0');
-    attribute ASYNC_REG              : string;
-    attribute ASYNC_REG of flipflops : signal is "true";
-begin
-
-    o <= flipflops(flipflops'high);
-
-    clk_proc : process(clk,flipflops,i)
-    begin
-        if rising_edge(clk) then
-            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
-        end if;
-    end process;
-
-end Behavioral;
diff --git a/smh-ac415-fpga/lcd_driver/video_ram.vhdl b/smh-ac415-fpga/lcd_driver/video_ram.vhdl
deleted file mode 100644
index 43bacaa..0000000
--- a/smh-ac415-fpga/lcd_driver/video_ram.vhdl
+++ /dev/null
@@ -1,232 +0,0 @@
--- megafunction wizard: %RAM: 2-PORT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: altsyncram 
-
--- ============================================================
--- File Name: video_ram.vhd
--- Megafunction Name(s):
--- 			altsyncram
---
--- Simulation Library Files(s):
--- 			altera_mf
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2013 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-LIBRARY altera_mf;
-USE altera_mf.all;
-
-ENTITY video_ram IS
-	PORT
-	(
-		data		: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-		rdaddress		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
-		rdclock		: IN STD_LOGIC ;
-		wraddress		: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
-		wrclock		: IN STD_LOGIC  := '1';
-		wren		: IN STD_LOGIC  := '0';
-		q		: OUT STD_LOGIC_VECTOR (1 DOWNTO 0)
-	);
-END video_ram;
-
-
-ARCHITECTURE SYN OF video_ram IS
-
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-
-
-
-	COMPONENT altsyncram
-	GENERIC (
-		address_aclr_b		: STRING;
-		address_reg_b		: STRING;
-		clock_enable_input_a		: STRING;
-		clock_enable_input_b		: STRING;
-		clock_enable_output_b		: STRING;
-		intended_device_family		: STRING;
-		lpm_type		: STRING;
-		numwords_a		: NATURAL;
-		numwords_b		: NATURAL;
-		operation_mode		: STRING;
-		outdata_aclr_b		: STRING;
-		outdata_reg_b		: STRING;
-		power_up_uninitialized		: STRING;
-		widthad_a		: NATURAL;
-		widthad_b		: NATURAL;
-		width_a		: NATURAL;
-		width_b		: NATURAL;
-		width_byteena_a		: NATURAL
-	);
-	PORT (
-			address_a	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
-			clock0	: IN STD_LOGIC ;
-			data_a	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			q_b	: OUT STD_LOGIC_VECTOR (1 DOWNTO 0);
-			wren_a	: IN STD_LOGIC ;
-			address_b	: IN STD_LOGIC_VECTOR (17 DOWNTO 0);
-			clock1	: IN STD_LOGIC 
-	);
-	END COMPONENT;
-
-BEGIN
-	q    <= sub_wire0(1 DOWNTO 0);
-
-	altsyncram_component : altsyncram
-	GENERIC MAP (
-		address_aclr_b => "NONE",
-		address_reg_b => "CLOCK1",
-		clock_enable_input_a => "BYPASS",
-		clock_enable_input_b => "BYPASS",
-		clock_enable_output_b => "BYPASS",
-		intended_device_family => "Cyclone IV E",
-		lpm_type => "altsyncram",
-		numwords_a => 206712,
-		numwords_b => 206712,
-		operation_mode => "DUAL_PORT",
-		outdata_aclr_b => "NONE",
-		outdata_reg_b => "CLOCK1",
-		power_up_uninitialized => "FALSE",
-		widthad_a => 18,
-		widthad_b => 18,
-		width_a => 2,
-		width_b => 2,
-		width_byteena_a => 1
-	)
-	PORT MAP (
-		address_a => wraddress,
-		clock0 => wrclock,
-		data_a => data,
-		wren_a => wren,
-		address_b => rdaddress,
-		clock1 => rdclock,
-		q_b => sub_wire0
-	);
-
-
-
-END SYN;
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
--- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
--- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
--- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
--- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
--- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
--- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
--- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
--- Retrieval info: PRIVATE: CLRq NUMERIC "0"
--- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
--- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
--- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
--- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
--- Retrieval info: PRIVATE: Clock NUMERIC "1"
--- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
--- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
--- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
--- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
--- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
--- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MEMSIZE NUMERIC "413424"
--- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
--- Retrieval info: PRIVATE: MIFfilename STRING ""
--- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
--- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
--- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
--- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
--- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
--- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
--- Retrieval info: PRIVATE: REGdata NUMERIC "1"
--- Retrieval info: PRIVATE: REGq NUMERIC "1"
--- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
--- Retrieval info: PRIVATE: REGrren NUMERIC "1"
--- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
--- Retrieval info: PRIVATE: REGwren NUMERIC "1"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
--- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
--- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
--- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "2"
--- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "2"
--- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "2"
--- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "2"
--- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
--- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
--- Retrieval info: PRIVATE: enable NUMERIC "0"
--- Retrieval info: PRIVATE: rden NUMERIC "0"
--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
--- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
--- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
--- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "206712"
--- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "206712"
--- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
--- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
--- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"
--- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "18"
--- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "18"
--- Retrieval info: CONSTANT: WIDTH_A NUMERIC "2"
--- Retrieval info: CONSTANT: WIDTH_B NUMERIC "2"
--- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
--- Retrieval info: USED_PORT: data 0 0 2 0 INPUT NODEFVAL "data[1..0]"
--- Retrieval info: USED_PORT: q 0 0 2 0 OUTPUT NODEFVAL "q[1..0]"
--- Retrieval info: USED_PORT: rdaddress 0 0 18 0 INPUT NODEFVAL "rdaddress[17..0]"
--- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
--- Retrieval info: USED_PORT: wraddress 0 0 18 0 INPUT NODEFVAL "wraddress[17..0]"
--- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
--- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
--- Retrieval info: CONNECT: @address_a 0 0 18 0 wraddress 0 0 18 0
--- Retrieval info: CONNECT: @address_b 0 0 18 0 rdaddress 0 0 18 0
--- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
--- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
--- Retrieval info: CONNECT: @data_a 0 0 2 0 data 0 0 2 0
--- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 2 0 @q_b 0 0 2 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL video_ram_inst.vhd TRUE
--- Retrieval info: LIB_FILE: altera_mf