1 files changed, 0 insertions, 169 deletions
diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
deleted file mode 100644
index 8a07fde..0000000
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
+++ /dev/null
@@ -1,169 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.NUMERIC_STD.all;
-
-entity lcd_driver is
-     port (
-        clk_50m : in std_logic;
-        sys_rst_n : in  std_logic;
-		
-		s_video : in std_logic;
-		s_bright : in std_logic;
-		s_hsync : in std_logic;
-		s_vsync : in std_logic;
-		
-		hdmi_ddc_scl : inout std_logic;
-		hdmi_ddc_sda : inout std_logic;
-
-		hdmi_clk : out std_logic;
-		hdmi_red : out std_logic;
-		hdmi_green : out std_logic;
-		hdmi_blue : out std_logic
-
-
-
---		hdmi_clk_p : out std_logic;
---		hdmi_clk_n : out std_logic;
---		hdmi_red_p : out std_logic;
---		hdmi_red_n : out std_logic;
---		hdmi_green_p : out std_logic;
---		hdmi_green_n : out std_logic;
---		hdmi_blue_p : out std_logic;
---		hdmi_blue_n : out std_logic
- );
-end entity lcd_driver;
-
-architecture behavioural of lcd_driver is
-
-	
-		signal wren :std_logic;
-	        signal w_addr :std_logic_vector(17 downto 0);
-		signal r_addr :std_logic_vector(17 downto 0);
-		
-		signal clk_80m : std_logic;
-		signal clk_20m : std_logic;
-		signal clk_91_25m : std_logic;
-	
-		signal a_bright: std_logic;
-		signal a_video: std_logic;
-		signal a_hsync: std_logic;
-		signal a_vsync : std_logic;
-
-
-		signal a_data : std_logic_vector(1 downto 0);
-
-		signal f_data : std_logic_vector(1 downto 0);
-
-		signal f_red : std_logic_vector(7 downto 0);
-		signal f_green : std_logic_vector(7 downto 0);
-		signal f_blue : std_logic_vector(7 downto 0);
-		signal f_hsync:  std_logic;
-		signal f_vsync : std_logic;
-
-		signal h_data : std_logic_vector(1 downto 0);
-	
-begin
-
-
--- gtf at 30Hz   xrandr --newmode "$M" 127.98  1536 1632 1792 2048  2048 2049 2052 2083  -HSync +Vsync
--- works at 60Hz xrandr --newmode "$M" 213.06  1536 1544 1552 1728  2048 2049 2051 2055  -HSync +Vsync
--- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
-
-
-     clk1_0:work.clk1
-	port map (
-		areset => not sys_rst_n,
-		inclk0 => clk_50m,
-		c0 => clk_80m,
-		c1 => clk_20m
-	);
-
-
-     clk2_0:work.clk2
-	port map (
-		areset => not sys_rst_n,
-		inclk0 => clk_50m,
-		c0 => clk_91_25m
-	);
-
-
-   
-	a_siggen0:work.a_siggen 
-	port map (
-	  sys_rst_n => sys_rst_n,
-		pclk => clk_20m,
-		bright=> a_bright,
-		video => a_video,
-		hsync => a_hsync,
-		vsync => a_vsync
-	);
-   
-
-
-	a_input0: work.a_input
-	port map (
-	  sys_rst_n => sys_rst_n,
-	  p_clk => clk_80m,
-	  
-	  video_in => a_video,
-	  bright_in => a_bright,
-	  hsync_in => a_hsync,
-	  vsync_in => a_vsync,
-	  
-	  video_out =>  a_data,
-	  addr_out  => w_addr,
-	  wren_out => wren
-	  );
-
-
-
-	formatter0: work.formatter
-	port map (
-	  sys_rst_n => sys_rst_n,
-	  p_clk => clk_91_25m,
-
-	  addr_out => r_addr,
-	  hsync_out => h_hsync,
-	  vsync_out => h_vsync,
-	  wren_out => wren
-	  );
-
-
-   
-	
-   process (sys_rst_n,r_addr,clk_91_25m)  begin 
-		if sys_rst_n = '0' then 
-			r_addr <=(others =>'0');
-		elsif rising_edge(clk_91_25m) then
-		   r_addr <= std_logic_vector(unsigned(w_addr)+1);
-		end if;
-	end process;
-	
-   vram: work.video_ram
-   PORT MAP (
-		data		=>a_data,
-		wraddress	=>w_addr,
-		wrclock		=>clk_80m,
-		wren		=> wren,
-		
-		rdaddress => r_addr,
-		rdclock	 => clk_91_25m,
-		q		=> h_data
-	);
-
-
-
-
-	
-
-	red_driver : work.hdmi_driver
-	PORT MAP (
-		in_h => h_data(0),
-		in_l => h_data(1),
-		clk => clk_91_25m,
-		output => hdmi_red
-	);
- 	
-	
-	
-end behavioural;