first cut at spartan 6 fpga

1 files changed, 80 insertions, 17 deletions

diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
index aeb8c0b..8a07fde 100644
--- a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
@@ -7,10 +7,10 @@ entity lcd_driver is
         clk_50m : in std_logic;
         sys_rst_n : in  std_logic;
 		
-		a_video : in std_logic;
-		a_bright : in std_logic;
-		a_hsync : in std_logic;
-		a_vsync : in std_logic;
+		s_video : in std_logic;
+		s_bright : in std_logic;
+		s_hsync : in std_logic;
+		s_vsync : in std_logic;
 		
 		hdmi_ddc_scl : inout std_logic;
 		hdmi_ddc_sda : inout std_logic;
@@ -21,6 +21,7 @@ entity lcd_driver is
 		hdmi_blue : out std_logic
 
 
+
 --		hdmi_clk_p : out std_logic;
 --		hdmi_clk_n : out std_logic;
 --		hdmi_red_p : out std_logic;
@@ -36,13 +37,30 @@ architecture behavioural of lcd_driver is
 
 	
 		signal wren :std_logic;
-      signal w_addr :std_logic_vector(17 downto 0);
+	        signal w_addr :std_logic_vector(17 downto 0);
 		signal r_addr :std_logic_vector(17 downto 0);
 		
-		signal a_clk : std_logic;
-		signal h_clk : std_logic;
-		signal h_data : std_logic_vector(1 downto 0);
+		signal clk_80m : std_logic;
+		signal clk_20m : std_logic;
+		signal clk_91_25m : std_logic;
+	
+		signal a_bright: std_logic;
+		signal a_video: std_logic;
+		signal a_hsync: std_logic;
+		signal a_vsync : std_logic;
+
+
 		signal a_data : std_logic_vector(1 downto 0);
+
+		signal f_data : std_logic_vector(1 downto 0);
+
+		signal f_red : std_logic_vector(7 downto 0);
+		signal f_green : std_logic_vector(7 downto 0);
+		signal f_blue : std_logic_vector(7 downto 0);
+		signal f_hsync:  std_logic;
+		signal f_vsync : std_logic;
+
+		signal h_data : std_logic_vector(1 downto 0);
 	
 begin
 
@@ -52,29 +70,71 @@ begin
 -- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
 
 
-   h_clk <= clk_50m;
+     clk1_0:work.clk1
+	port map (
+		areset => not sys_rst_n,
+		inclk0 => clk_50m,
+		c0 => clk_80m,
+		c1 => clk_20m
+	);
+
+
+     clk2_0:work.clk2
+	port map (
+		areset => not sys_rst_n,
+		inclk0 => clk_50m,
+		c0 => clk_91_25m
+	);
+
+
+   
+	a_siggen0:work.a_siggen 
+	port map (
+	  sys_rst_n => sys_rst_n,
+		pclk => clk_20m,
+		bright=> a_bright,
+		video => a_video,
+		hsync => a_hsync,
+		vsync => a_vsync
+	);
    
-	a_inpuut0: work.a_input
+
+
+	a_input0: work.a_input
 	port map (
 	  sys_rst_n => sys_rst_n,
-	  clk_50m => clk_50m,
+	  p_clk => clk_80m,
 	  
 	  video_in => a_video,
 	  bright_in => a_bright,
 	  hsync_in => a_hsync,
 	  vsync_in => a_vsync,
 	  
-	  p_clk_out => a_clk,
 	  video_out =>  a_data,
 	  addr_out  => w_addr,
 	  wren_out => wren
 	  );
 
+
+
+	formatter0: work.formatter
+	port map (
+	  sys_rst_n => sys_rst_n,
+	  p_clk => clk_91_25m,
+
+	  addr_out => r_addr,
+	  hsync_out => h_hsync,
+	  vsync_out => h_vsync,
+	  wren_out => wren
+	  );
+
+
+   
 	
-   process (sys_rst_n,r_addr,h_clk)  begin 
+   process (sys_rst_n,r_addr,clk_91_25m)  begin 
 		if sys_rst_n = '0' then 
 			r_addr <=(others =>'0');
-		elsif rising_edge(h_clk) then
+		elsif rising_edge(clk_91_25m) then
 		   r_addr <= std_logic_vector(unsigned(w_addr)+1);
 		end if;
 	end process;
@@ -83,21 +143,24 @@ begin
    PORT MAP (
 		data		=>a_data,
 		wraddress	=>w_addr,
-		wrclock		=>a_clk,
+		wrclock		=>clk_80m,
 		wren		=> wren,
 		
 		rdaddress => r_addr,
-		rdclock	 => h_clk,
+		rdclock	 => clk_91_25m,
 		q		=> h_data
 	);
 
+
+
+
 	
 
 	red_driver : work.hdmi_driver
 	PORT MAP (
 		in_h => h_data(0),
 		in_l => h_data(1),
-		clk => h_clk,
+		clk => clk_91_25m,
 		output => hdmi_red
 	);