add noddy cyclone IV fpga design

1 files changed, 106 insertions, 0 deletions

diff --git a/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
new file mode 100644
index 0000000..aeb8c0b
--- /dev/null
+++ b/smh-ac415-fpga/lcd_driver/lcd_driver.vhdl
@@ -0,0 +1,106 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity lcd_driver is
+     port (
+        clk_50m : in std_logic;
+        sys_rst_n : in  std_logic;
+		
+		a_video : in std_logic;
+		a_bright : in std_logic;
+		a_hsync : in std_logic;
+		a_vsync : in std_logic;
+		
+		hdmi_ddc_scl : inout std_logic;
+		hdmi_ddc_sda : inout std_logic;
+
+		hdmi_clk : out std_logic;
+		hdmi_red : out std_logic;
+		hdmi_green : out std_logic;
+		hdmi_blue : out std_logic
+
+
+--		hdmi_clk_p : out std_logic;
+--		hdmi_clk_n : out std_logic;
+--		hdmi_red_p : out std_logic;
+--		hdmi_red_n : out std_logic;
+--		hdmi_green_p : out std_logic;
+--		hdmi_green_n : out std_logic;
+--		hdmi_blue_p : out std_logic;
+--		hdmi_blue_n : out std_logic
+ );
+end entity lcd_driver;
+
+architecture behavioural of lcd_driver is
+
+	
+		signal wren :std_logic;
+      signal w_addr :std_logic_vector(17 downto 0);
+		signal r_addr :std_logic_vector(17 downto 0);
+		
+		signal a_clk : std_logic;
+		signal h_clk : std_logic;
+		signal h_data : std_logic_vector(1 downto 0);
+		signal a_data : std_logic_vector(1 downto 0);
+	
+begin
+
+
+-- gtf at 30Hz   xrandr --newmode "$M" 127.98  1536 1632 1792 2048  2048 2049 2052 2083  -HSync +Vsync
+-- works at 60Hz xrandr --newmode "$M" 213.06  1536 1544 1552 1728  2048 2049 2051 2055  -HSync +Vsync
+-- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
+
+
+   h_clk <= clk_50m;
+   
+	a_inpuut0: work.a_input
+	port map (
+	  sys_rst_n => sys_rst_n,
+	  clk_50m => clk_50m,
+	  
+	  video_in => a_video,
+	  bright_in => a_bright,
+	  hsync_in => a_hsync,
+	  vsync_in => a_vsync,
+	  
+	  p_clk_out => a_clk,
+	  video_out =>  a_data,
+	  addr_out  => w_addr,
+	  wren_out => wren
+	  );
+
+	
+   process (sys_rst_n,r_addr,h_clk)  begin 
+		if sys_rst_n = '0' then 
+			r_addr <=(others =>'0');
+		elsif rising_edge(h_clk) then
+		   r_addr <= std_logic_vector(unsigned(w_addr)+1);
+		end if;
+	end process;
+	
+   vram: work.video_ram
+   PORT MAP (
+		data		=>a_data,
+		wraddress	=>w_addr,
+		wrclock		=>a_clk,
+		wren		=> wren,
+		
+		rdaddress => r_addr,
+		rdclock	 => h_clk,
+		q		=> h_data
+	);
+
+	
+
+	red_driver : work.hdmi_driver
+	PORT MAP (
+		in_h => h_data(0),
+		in_l => h_data(1),
+		clk => h_clk,
+		output => hdmi_red
+	);
+ 	
+	
+	
+end behavioural;