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authorroot <root@new-fish.medaka.james.internal>2025-04-30 23:46:52 +0100
committerroot <root@new-fish.medaka.james.internal>2025-04-30 23:46:52 +0100
commit888b91e6fd42c12052af950b63479e97992bd85c (patch)
treea955d9c5038471c2de76fd46ab3d1cb6fb4c5932 /smh-ac415-fpga/lcd_driver/debounce.vhdl
parentcff444eb1bd7bc498bc50dca506b745317bc3494 (diff)
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diff --git a/smh-ac415-fpga/lcd_driver/debounce.vhdl b/smh-ac415-fpga/lcd_driver/debounce.vhdl
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--- a/smh-ac415-fpga/lcd_driver/debounce.vhdl
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-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-
-entity debounce is
- generic (stages : natural := 1);
- port (clk : in std_logic;
- i : in std_logic;
- o : out std_logic);
-end debounce;
-
-architecture Behavioral of debounce is
- signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
- constant zero : std_logic_vector(stages-1 downto 0) := (others => '0');
- constant one : std_logic_vector(stages-1 downto 0) := (others => '1');
- signal output : std_logic := '0';
-begin
-
- o <= output;
-
- process (clk,flipflops,i)
- begin
- if rising_edge(clk) then
- flipflops <= flipflops(flipflops'high-1 downto 0) & i;
- if flipflops = one and i = '1' then
- output <= '1';
- elsif flipflops = zero and i = '0' then
- output <= '0';
- end if;
- end if;
- end process;
-
-end architecture;