working serial ports

3 files changed, 11 insertions, 4 deletions

diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl
index 9666b4a..01bdbce 100644
--- a/fpga/hp_lcd_driver/kbd_uarts.vhdl
+++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl
@@ -244,7 +244,7 @@ axi_protocol_converter_0_i: entity work.axi_protocol_converter_0
 
             ip2intc_irpt  => u0_int,
             freeze        => '0',
-            sin           => u1_tx,
+            sin           => u0_rx,
             sout          => u0_tx,
             ctsn	  => '0',
 	  dcdn		  =>'0',
@@ -290,7 +290,7 @@ axi_protocol_converter_0_i: entity work.axi_protocol_converter_0
 
             ip2intc_irpt  => u1_int,
             freeze        => '0',
-            sin           => u0_tx,
+            sin           => u1_rx,
             sout          => u1_tx,
             ctsn	  => '0',
 	  dcdn		  =>'0',
diff --git a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
index 823fd0c..4e0b618 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/processing_system7_0.tcl
@@ -36,6 +36,7 @@ set_property -dict [list \
 	CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J128M16 HA-15E} \
 	CONFIG.PCW_USE_FABRIC_INTERRUPT {1} \
 	CONFIG.PCW_IRQ_F2P_INTR {1} \
+	CONFIG.PCW_NUM_F2P_INTR_INPUTS {2} \
 	CONFIG.PCW_NAND_PERIPHERAL_ENABLE {1} \
 	CONFIG.PCW_NAND_NAND_IO {MIO 0 2.. 14} \
 	CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 5d0d3e5..2319b08 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -213,6 +213,8 @@ architecture arch of zynq7_wrapper is
     signal hp0_wvalid  : std_logic;
     signal hp0_wstrb   : std_logic_vector(7 downto 0);
 
+    signal pl_irqs	: std_logic_vector(1 downto 0);
+
 
     signal run : std_logic;
 
@@ -458,7 +460,9 @@ begin
             S_AXI_HP0_WLAST   => '1',
             S_AXI_HP0_WREADY  => hp0_wready,
             S_AXI_HP0_WSTRB   => hp0_wstrb,
-            S_AXI_HP0_WVALID  => hp0_wvalid
+            S_AXI_HP0_WVALID  => hp0_wvalid,
+
+  	    IRQ_F2P	      => pl_irqs
             );
 
     eth0_mdio_mdio_iobuf : IOBUF
@@ -599,7 +603,9 @@ begin
             u0_tx => u0_tx,
             u0_rx => u0_rx,
             u1_tx => u1_tx,
-            u1_rx => u1_rx
+            u1_rx => u1_rx,
+	    u0_int => pl_irqs(0),
+	    u1_int => pl_irqs(1)
             );