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| author | root <root@new-fish.medaka.james.internal> | 2025-11-16 02:04:11 +0000 |
|---|---|---|
| committer | root <root@new-fish.medaka.james.internal> | 2025-11-16 02:04:11 +0000 |
| commit | aaaffdae114dd0bc086706d209dd358ac623bca8 (patch) | |
| tree | 30739a52a2f26e86055078d4dd4fd34612537d66 /fpga/hp_lcd_driver | |
| parent | d742c2c0cc373ce66bfdad36d05b7cf2ab6a5ea2 (diff) | |
| download | hp_instrument_lcds-aaaffdae114dd0bc086706d209dd358ac623bca8.tar.gz hp_instrument_lcds-aaaffdae114dd0bc086706d209dd358ac623bca8.tar.bz2 hp_instrument_lcds-aaaffdae114dd0bc086706d209dd358ac623bca8.zip | |
working corssbar
Diffstat (limited to 'fpga/hp_lcd_driver')
| -rw-r--r-- | fpga/hp_lcd_driver/kbd_uarts.vhdl | 2 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl | 4 |
2 files changed, 4 insertions, 2 deletions
diff --git a/fpga/hp_lcd_driver/kbd_uarts.vhdl b/fpga/hp_lcd_driver/kbd_uarts.vhdl index 25ad81e..9666b4a 100644 --- a/fpga/hp_lcd_driver/kbd_uarts.vhdl +++ b/fpga/hp_lcd_driver/kbd_uarts.vhdl @@ -169,6 +169,7 @@ axi_protocol_converter_0_i: entity work.axi_protocol_converter_0 m_axi_rready => m_axi_rready ); + axi_crossbar_0_i : entity work.axi_crossbar_0 port map ( aclk => s_axi_aclk, @@ -217,6 +218,7 @@ axi_protocol_converter_0_i: entity work.axi_protocol_converter_0 + axi_uart16550_0_i0 : entity work.axi_uart16550_0 port map ( s_axi_aclk => s_axi_aclk, diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl index b24f354..178b06a 100644 --- a/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl +++ b/fpga/hp_lcd_driver/zynq7_ip/axi_crossbar_0.tcl @@ -16,7 +16,7 @@ set_property -dict [list \ CONFIG.DATA_WIDTH {32} \ CONFIG.ID_WIDTH {0} \ CONFIG.M00_A00_ADDR_WIDTH {12} \ - CONFIG.M00_A00_BASE_ADDR {0x0000000000000000} \ + CONFIG.M00_A00_BASE_ADDR {0x80000000} \ CONFIG.M00_ERR_MODE {0} \ CONFIG.M00_READ_ISSUING {1} \ CONFIG.M00_S00_READ_CONNECTIVITY {1} \ @@ -24,7 +24,7 @@ set_property -dict [list \ CONFIG.M00_SECURE {0} \ CONFIG.M00_WRITE_ISSUING {1} \ CONFIG.M01_A00_ADDR_WIDTH {12} \ - CONFIG.M01_A00_BASE_ADDR {0x0000000000001000} \ + CONFIG.M01_A00_BASE_ADDR {0x80001000} \ CONFIG.M01_ERR_MODE {0} \ CONFIG.M01_READ_ISSUING {1} \ CONFIG.M01_S00_READ_CONNECTIVITY {1} \ |