tidy up smh-ac415

5 files changed, 59 insertions, 69 deletions

diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
index 0c5b28f..3309d00 100644
--- a/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
@@ -17,45 +17,42 @@ end clkgen;
 architecture Behavioural of clkgen is
 
     signal clkfbout   : std_logic;
-    signal clk_100m   : std_logic;
-    signal clk_80m    : std_logic;
-    signal clk_40m    : std_logic;
-    signal clk_20m    : std_logic;
+    signal clk_120m   : std_logic;
+    signal clk_78_642m : std_logic;
+    signal clk_48m    : std_logic;
+    signal clk_24m    : std_logic;
     signal pll_locked : std_logic;
 
     signal reset : std_logic;
 begin
 
-    clkgen_impl0 : entity work.clkgen_cyclone4_impl
+     clkgen_a : entity work.clkgen_cyclone4_a_impl
         port map (
             areset => not sys_rst_n,
             inclk0 => clk_in,
-            c0     => clk_100m,
-            c1     => clk_80m,
-            c2     => clk_40m,
-            c3     => clk_20m,
-            locked => pll_locked);
+            c0     => clk_78_642m,
+            locked => open);
+
 
-    o_clk <= clk_20m;
---    o_clk_buf : BUFG port map (
---        I => clk_20m,
---        O => o_clk);
---
+    i_clk <= clk_78_642m;
+
+    clkgen_b : entity work.clkgen_cyclone4_b_impl
+        port map (
+            areset => not sys_rst_n,
+            inclk0 => clk_in,
+            c0     => clk_120m,
+            c1     => open,
+            c2     => clk_48m,
+            c3     => clk_24m,
+            locked => pll_locked);
 
-    o_clk_x2 <= clk_40m;
+    o_clk <= clk_24m;
 
---    o_clk_x2_buf : BUFG port map (
---        I => clk_40m,
---        O => o_clk_x2);
---
+    -- not used in the cyclone design
+    o_clk_x2 <= clk_48m;
 
-    i_clk <= clk_80m;
---    i_clk_buf : BUFG port map (
---        I => clk_80m,
---        O => i_clk);
---
 
-    o_clk_phy <= clk_100m;
+    o_clk_phy <= clk_120m;
 
     locked <= pll_locked;
 
diff --git a/fpga/hp_lcd_driver/input_pll.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl
index 8c877af..a5bcb9d 100644
--- a/fpga/hp_lcd_driver/input_pll.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4_a_impl.vhdl
@@ -4,7 +4,7 @@
 -- MODULE: altpll 
 
 -- ============================================================
--- File Name: input_pll.vhd
+-- File Name: clkgen_cyclone4_a_impl.vhd
 -- Megafunction Name(s):
 -- 			altpll
 --
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
 LIBRARY altera_mf;
 USE altera_mf.all;
 
-ENTITY input_pll IS
+ENTITY clkgen_cyclone4_a_impl IS
 	PORT
 	(
 		areset		: IN STD_LOGIC  := '0';
@@ -47,10 +47,10 @@ ENTITY input_pll IS
 		c0		: OUT STD_LOGIC ;
 		locked		: OUT STD_LOGIC 
 	);
-END input_pll;
+END clkgen_cyclone4_a_impl;
 
 
-ARCHITECTURE SYN OF input_pll IS
+ARCHITECTURE SYN OF clkgen_cyclone4_a_impl IS
 
 	SIGNAL sub_wire0	: STD_LOGIC ;
 	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (4 DOWNTO 0);
@@ -147,7 +147,7 @@ BEGIN
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 20000,
 		intended_device_family => "Cyclone IV E",
-		lpm_hint => "CBX_MODULE_PREFIX=input_pll",
+		lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_a_impl",
 		lpm_type => "altpll",
 		operation_mode => "NORMAL",
 		pll_type => "AUTO",
@@ -270,7 +270,7 @@ END SYN;
 -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "input_pll.mif"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen_cyclone4_a_impl.mif"
 -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
@@ -355,11 +355,11 @@ END SYN;
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL input_pll.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL input_pll.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL input_pll.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL input_pll.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL input_pll.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL input_pll_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_a_impl.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_a_impl.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_a_impl.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_a_impl.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_a_impl.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_a_impl_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: altera_mf
 -- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4_impl.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4_b_impl.vhdl
index 5a60e85..9a51b3a 100644
--- a/fpga/hp_lcd_driver/clkgen_cyclone4_impl.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4_b_impl.vhdl
@@ -4,7 +4,7 @@
 -- MODULE: altpll 
 
 -- ============================================================
--- File Name: clkgen_cyclone4_impl.vhd
+-- File Name: clkgen_cyclone4_b_impl.vhd
 -- Megafunction Name(s):
 -- 			altpll
 --
@@ -39,7 +39,7 @@ USE ieee.std_logic_1164.all;
 LIBRARY altera_mf;
 USE altera_mf.all;
 
-ENTITY clkgen_cyclone4_impl IS
+ENTITY clkgen_cyclone4_b_impl IS
 	PORT
 	(
 		areset		: IN STD_LOGIC  := '0';
@@ -50,10 +50,10 @@ ENTITY clkgen_cyclone4_impl IS
 		c3		: OUT STD_LOGIC ;
 		locked		: OUT STD_LOGIC 
 	);
-END clkgen_cyclone4_impl;
+END clkgen_cyclone4_b_impl;
 
 
-ARCHITECTURE SYN OF clkgen_cyclone4_impl IS
+ARCHITECTURE SYN OF clkgen_cyclone4_b_impl IS
 
 	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
 	SIGNAL sub_wire1	: STD_LOGIC ;
@@ -183,7 +183,7 @@ BEGIN
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 20000,
 		intended_device_family => "Cyclone IV E",
-		lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_impl",
+		lpm_hint => "CBX_MODULE_PREFIX=clkgen_cyclone4_b_impl",
 		lpm_type => "altpll",
 		operation_mode => "NORMAL",
 		pll_type => "AUTO",
@@ -339,7 +339,7 @@ END SYN;
 -- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 -- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen_cyclone4_impl.mif"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clkgen_cyclone4_b_impl.mif"
 -- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
@@ -451,11 +451,11 @@ END SYN;
 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 -- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
--- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.vhd TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.ppf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.inc FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl.bsf FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_impl_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_b_impl.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_b_impl.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_b_impl.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_b_impl.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_b_impl.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL clkgen_cyclone4_b_impl_inst.vhd FALSE
 -- Retrieval info: LIB_FILE: altera_mf
 -- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index a8cf948..e1625ba 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -63,17 +63,22 @@ begin
 
 
 -- clocking:
--- i_clk is 4*20MHz to give us 4 choices of sampling position
+-- i_clk is 4*(nominal) 20MHz to give us 4 choices of sampling position
 -- o_clk is the output pixel clock
 -- o_clk_x2 is used by the spartan serdes
 -- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10)
 
-    i_clkgen : entity work.input_pll
+    clkgen : entity work.clkgen
         port map (
-            areset => open,
-            inclk0 => clk_50m,
-            c0     => i_clk,
-            locked => open);
+            sys_rst_n => sys_rst_n,
+            clk_in    => clk_50m,
+            i_clk     => i_clk,
+            o_clk     => o_clk,
+            o_clk_x2  => o_clk_x2,
+            o_clk_phy => o_clk_phy,
+            locked    => clk_locked
+            );
+
 
 
     process (i_clk, sys_rst_n)
@@ -105,18 +110,6 @@ begin
 
     i_clk_out <= epk;
 
-    clkgen : entity work.clkgen
-        port map (
-            sys_rst_n => sys_rst_n,
-            clk_in    => clk_50m,
-            i_clk     => open,
-            o_clk     => o_clk,
-            o_clk_x2  => o_clk_x2,
-            o_clk_phy => o_clk_phy,
-            locked    => clk_locked
-            );
-
-    --i_clk_out <= i_clk;
 
     input0 : entity work.input_stage
         generic map(
diff --git a/fpga/hp_lcd_driver/smh-ac415.mk b/fpga/hp_lcd_driver/smh-ac415.mk
index 52e23e7..0d37eb7 100644
--- a/fpga/hp_lcd_driver/smh-ac415.mk
+++ b/fpga/hp_lcd_driver/smh-ac415.mk
@@ -9,7 +9,7 @@ OF=output_files
 
 PROJECT = hp_lcd_driver
 VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl  output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
-IPS= vram_cyclone4_impl.vhdl  clkgen_cyclone4_impl.vhdl input_pll.vhdl
+IPS= vram_cyclone4_impl.vhdl  clkgen_cyclone4_a_impl.vhdl clkgen_cyclone4_b_impl.vhdl
 
 DESIGN_NAME=${TOP}