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| author | root <root@new-fish.medaka.james.internal> | 2025-11-19 15:43:32 +0000 |
|---|---|---|
| committer | root <root@new-fish.medaka.james.internal> | 2025-11-19 15:43:43 +0000 |
| commit | c9f8fc95ec1f3e5c9f7bfd79df47272ba43ad8d0 (patch) | |
| tree | 73c2de1e4a0f200de2173c047b111de3fa20a406 /fpga/hp_lcd_driver | |
| parent | 6f023a74593e3cf0107ff88d1c0c1ccf205d46d0 (diff) | |
| download | hp_instrument_lcds-c9f8fc95ec1f3e5c9f7bfd79df47272ba43ad8d0.tar.gz hp_instrument_lcds-c9f8fc95ec1f3e5c9f7bfd79df47272ba43ad8d0.tar.bz2 hp_instrument_lcds-c9f8fc95ec1f3e5c9f7bfd79df47272ba43ad8d0.zip | |
Diffstat (limited to 'fpga/hp_lcd_driver')
| -rw-r--r-- | fpga/hp_lcd_driver/fb_hw.vhdl | 21 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl | 10 |
2 files changed, 15 insertions, 16 deletions
diff --git a/fpga/hp_lcd_driver/fb_hw.vhdl b/fpga/hp_lcd_driver/fb_hw.vhdl index f4adbc9..248c2ef 100644 --- a/fpga/hp_lcd_driver/fb_hw.vhdl +++ b/fpga/hp_lcd_driver/fb_hw.vhdl @@ -76,7 +76,7 @@ architecture Behavioural of fb_hw is signal overlay_demux_p : integer; signal overlay_demux : integer; - signal overlay_data : integer; + signal overlay_data : std_logic_vector(7 downto 0); signal fb_ps_clk : std_logic; @@ -86,7 +86,7 @@ architecture Behavioural of fb_hw is signal fb_ps_wrdata : std_logic_vector (31 downto 0); signal fb_ps_rddata : std_logic_vector (31 downto 0); - signal fb_pl_addr : std_logic_vector (14 downto 0); + signal fb_pl_addr : std_logic_vector (15 downto 0); signal fb_pl_rddata : std_logic_vector (31 downto 0); begin @@ -111,7 +111,7 @@ begin clka => fb_ps_clk, ena => fb_ps_en, wea => fb_ps_we, - addra => fb_ps_addr (16 downto 2), + addra => fb_ps_addr (17 downto 2), dina => fb_ps_wrdata, douta => fb_ps_rddata, clkb => overlay_clk, @@ -123,26 +123,25 @@ begin - fb_pl_addr <= overlay_addr(17 downto 3); + fb_pl_addr <= overlay_addr(17 downto 2); process (overlay_clk) begin if rising_edge(overlay_clk) then - overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4; + overlay_demux_p <= to_integer(unsigned(overlay_addr(1 downto 0)))*8; overlay_demux <= overlay_demux_p; end if; end process; - overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux))); + overlay_data <= fb_pl_rddata(overlay_demux+7 downto overlay_demux); overlay_gate <= '0' when overlay_off='1' else '1' when overlay_on='1' else - '0' when overlay_data = 0 else '1'; - - overlay_r <= r_lut(overlay_data); - overlay_g <= g_lut(overlay_data); - overlay_b <= b_lut(overlay_data); + '0' when overlay_data = x"00" else '1'; + overlay_r <= x"ff" when overlay_data(7) else x"00"; + overlay_g <= x"ff" when overlay_data(4) else x"00"; + overlay_b <= x"ff" when overlay_data(1) else x"00"; axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0 port map ( diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl index aefd1f9..57f0b3e 100644 --- a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl +++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl @@ -12,12 +12,12 @@ set_property -dict [list \ CONFIG.Memory_Type {True_Dual_Port_RAM} \ CONFIG.Use_Byte_Write_Enable {false} \ CONFIG.Byte_Size {9} \ - CONFIG.Write_Width_A {6} \ - CONFIG.Write_Depth_A {30720} \ - CONFIG.Read_Width_A {6} \ + CONFIG.Write_Width_A {3} \ + CONFIG.Write_Depth_A {61440} \ + CONFIG.Read_Width_A {3} \ CONFIG.Operating_Mode_A {WRITE_FIRST} \ - CONFIG.Write_Width_B {6} \ - CONFIG.Read_Width_B {6} \ + CONFIG.Write_Width_B {3} \ + CONFIG.Read_Width_B {3} \ CONFIG.Operating_Mode_B {READ_FIRST} \ CONFIG.Enable_B {Always_Enabled} \ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \ |