working 3bpp fbHEADmaster

5 files changed, 28 insertions, 47 deletions

diff --git a/fpga/ebaz4205/src/ebaz4205-board.dtsi b/fpga/ebaz4205/src/ebaz4205-board.dtsi
index 80733a0..324e4a7 100644
--- a/fpga/ebaz4205/src/ebaz4205-board.dtsi
+++ b/fpga/ebaz4205/src/ebaz4205-board.dtsi
@@ -1,8 +1,10 @@
 / {
+/*
         chosen {
                 bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rw";
                 stdout-path = "serial0:115200n8";
         };
+*/
 
         aliases {
                 ethernet0 = &gem0;
@@ -31,6 +33,7 @@
 		};
 	};
 
+/*
         buttons {
                 compatible = "gpio-keys-polled";
                 poll-interval = <100>;
@@ -50,6 +53,7 @@
                         autorepeat;
                 };
         };
+*/
 };
 
 &clkc {
diff --git a/fpga/ebaz4205/src/ebaz4205-zynq7.dts b/fpga/ebaz4205/src/ebaz4205-zynq7.dts
index daa52df..2f70a82 100644
--- a/fpga/ebaz4205/src/ebaz4205-zynq7.dts
+++ b/fpga/ebaz4205/src/ebaz4205-zynq7.dts
@@ -6,19 +6,6 @@
 };
 
 
-//&amba  {
-//	ocm: sram@fffc0000 {
-//                compatible = "mmio-sram";
-//                reg = <0xfffc0000 0x10000>;
-//                #address-cells = <1>;
-//                #size-cells = <1>;
-//                ranges = <0 0xfffc0000 0x10000>;
-//                ocm-sram@0 {
-//                        reg = <0x0 0x10000>;
-//                };
-//	}
-//};
-
 
 &ocm {
         compatible = "jmm,video-capture-device";
@@ -28,22 +15,21 @@
 };
 
 &amba {
-		plfb: sram@40000000 {
-//			status = "okay";
+		plfb: plfb@40000000 {
 		        compatible = "jmm,frame-buffer-device";
 			reg = <0x40000000 0x40000>;
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 0x40000000 0x40000>;
 			rotation=<90>;
-			plfb@0 {
-				rotation=<90>;
-				reg = <0x0 0x40000>;
-			};
+
+			gpios = <&gpio0 57 0>,
+				<&gpio0 58 0>;
+
+
 		};
 
 		uart2: serial@80000000 {
-//			compatible = "jmm,serial-test";
 			compatible = "ns16550";
 			status = "okay";
 			reg = <0x80000000 0x1000>;
@@ -55,7 +41,6 @@
 			interrupts = <0 29 4>;
 		};
 		uart3: serial@80001000 {
-//			compatible = "jmm,serial-test";
 			compatible = "ns16550";
 			status = "okay";
 			reg = <0x80001000 0x1000>;
@@ -73,10 +58,3 @@
 
 
 
-
-
-//&clkc {
-//	fclk-enable = <0xf>;
-//	ps-clk-frequency = <666666666>;
-//};
-
diff --git a/fpga/ebaz4205/src/uEnv.txt b/fpga/ebaz4205/src/uEnv.txt
index d881b54..95f9779 100644
--- a/fpga/ebaz4205/src/uEnv.txt
+++ b/fpga/ebaz4205/src/uEnv.txt
@@ -1,14 +1,14 @@
-ethaddr=00:01:02:03:04:05
 machine_name=ebaz4205-zynq7
 kernel_image=uImage
+setmac=load mmc 0 ${ramdisk_load_address} mac.txt && env import -t ${ramdisk_load_address} ${filesize}
 loadkernel=load mmc 0 ${kernel_load_address} ${kernel_image}
 devicetree_image=ebaz4205-zynq7.dtb
 loaddtb=load mmc 0 ${devicetree_load_address} ${devicetree_image}
 ramdisk_image=nowt.cpio.uboot
 loadramdisk=load mmc 0 ${ramdisk_load_address} ${ramdisk_image}
 notbootargs=earlyprintk console=ttyPS0,115200 root=/dev/mmcblk0p3 ro rootwait
-bootargs=console=tty0 root=/dev/mmcblk0p3 ro rootwait
+bootargs=root=/dev/mmcblk0p3 ro rootwait
 bitstream_image=hp_lcd_driver.bin
 bitstream_type=load
 fpga_config=fpga ${bitstream_type} 0 ${bitstream_load_address} ${filesize}
-sdboot=if mmcinfo; then run leds_bootstate_0;run uenvboot;echo Copying Linux from SD to RAM...; run mmc_loadkernel && run mmc_loaddtb && run mmc_loadramdisk && run mmc_loadfpga && run leds_bootstate_1; echo Configure FPGA...; run fpga_config && run leds_bootstate_2; echo Handoff to Linux kernel...;bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}; fi
+sdboot=if mmcinfo; then run leds_bootstate_0;run uenvboot;echo Setting MAC address...; run setmac ; echo Copying Linux from SD to RAM...; run mmc_loadkernel && run mmc_loaddtb && run mmc_loadramdisk && run mmc_loadfpga && run leds_bootstate_1; echo Configure FPGA...; run fpga_config && run leds_bootstate_2; echo Handoff to Linux kernel...;bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}; fi
diff --git a/fpga/hp_lcd_driver/fb_hw.vhdl b/fpga/hp_lcd_driver/fb_hw.vhdl
index f4adbc9..248c2ef 100644
--- a/fpga/hp_lcd_driver/fb_hw.vhdl
+++ b/fpga/hp_lcd_driver/fb_hw.vhdl
@@ -76,7 +76,7 @@ architecture Behavioural of fb_hw is
 
     signal overlay_demux_p : integer;
     signal overlay_demux   : integer;
-    signal overlay_data    : integer;
+    signal overlay_data    : std_logic_vector(7 downto 0);
 
 
     signal fb_ps_clk    : std_logic;
@@ -86,7 +86,7 @@ architecture Behavioural of fb_hw is
     signal fb_ps_wrdata : std_logic_vector (31 downto 0);
     signal fb_ps_rddata : std_logic_vector (31 downto 0);
 
-    signal fb_pl_addr   : std_logic_vector (14 downto 0);
+    signal fb_pl_addr   : std_logic_vector (15 downto 0);
     signal fb_pl_rddata : std_logic_vector (31 downto 0);
 
 begin
@@ -111,7 +111,7 @@ begin
             clka  => fb_ps_clk,
             ena   => fb_ps_en,
             wea   => fb_ps_we,
-            addra => fb_ps_addr (16 downto 2),
+            addra => fb_ps_addr (17 downto 2),
             dina  => fb_ps_wrdata,
             douta => fb_ps_rddata,
             clkb  => overlay_clk,
@@ -123,26 +123,25 @@ begin
 
 
 
-    fb_pl_addr <= overlay_addr(17 downto 3);
+    fb_pl_addr <= overlay_addr(17 downto 2);
 
     process (overlay_clk)
     begin
         if rising_edge(overlay_clk) then
-            overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4;
+            overlay_demux_p <= to_integer(unsigned(overlay_addr(1 downto 0)))*8;
             overlay_demux   <= overlay_demux_p;
         end if;
     end process;
 
-    overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux)));
+    overlay_data <= fb_pl_rddata(overlay_demux+7 downto overlay_demux);
 
     overlay_gate <= '0' when overlay_off='1' else
 		    '1' when overlay_on='1' else
-		    '0' when overlay_data = 0 else '1';
-
-    overlay_r    <= r_lut(overlay_data);
-    overlay_g    <= g_lut(overlay_data);
-    overlay_b    <= b_lut(overlay_data);
+		    '0' when overlay_data = x"00" else '1';
 
+    overlay_r    <= x"ff" when overlay_data(7)  else x"00";
+    overlay_g    <= x"ff" when overlay_data(4)  else x"00";
+    overlay_b    <= x"ff" when overlay_data(1)  else x"00";
 
     axi_bram_ctrl_0_i : entity work.axi_bram_ctrl_0
         port map (
diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
index aefd1f9..57f0b3e 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
@@ -12,12 +12,12 @@ set_property -dict [list  \
 	CONFIG.Memory_Type {True_Dual_Port_RAM}  \
 	CONFIG.Use_Byte_Write_Enable {false}  \
 	CONFIG.Byte_Size {9}  \
-	CONFIG.Write_Width_A {6}  \
-	CONFIG.Write_Depth_A {30720}  \
-	CONFIG.Read_Width_A {6}  \
+	CONFIG.Write_Width_A {3}  \
+	CONFIG.Write_Depth_A {61440}  \
+	CONFIG.Read_Width_A {3}  \
 	CONFIG.Operating_Mode_A {WRITE_FIRST}  \
-	CONFIG.Write_Width_B {6}  \
-	CONFIG.Read_Width_B {6}  \
+	CONFIG.Write_Width_B {3}  \
+	CONFIG.Read_Width_B {3}  \
 	CONFIG.Operating_Mode_B {READ_FIRST}  \
 	CONFIG.Enable_B {Always_Enabled}  \
 	CONFIG.Register_PortA_Output_of_Memory_Primitives {false}  \