fix uart clock

5 files changed, 113 insertions, 7 deletions

diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 0558bdd..9b9fe65 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,4 +1,4 @@
-DIP=10.16.66.234
+DIP=10.16.66.224
 #TARGETS=rando_a7
 TARGETS=ebaz4205
 #TARGETS= ebaz4205 #rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
diff --git a/fpga/hp_lcd_driver/ebaz4205.xdc b/fpga/hp_lcd_driver/ebaz4205.xdc
index c2ee09d..9d345be 100644
--- a/fpga/hp_lcd_driver/ebaz4205.xdc
+++ b/fpga/hp_lcd_driver/ebaz4205.xdc
@@ -117,14 +117,14 @@ set_property IOSTANDARD LVCMOS33 [get_ports {hsync_in}]
 #set_property PULLTYPE PULLUP [get_ports {sys_rst_n}]
 #		
 
-set_property PACKAGE_PIN M19 [get_ports {u0_tx}]; #data3-5
-set_property IOSTANDARD LVCMOS33 [get_ports {u0_tx}]
-set_property PACKAGE_PIN P18 [get_ports {u0_rx}]; #data3-7
-set_property IOSTANDARD LVCMOS33 [get_ports {u0_rx}]
-set_property PACKAGE_PIN N17 [get_ports {u1_tx}]; #data3-9
+set_property PACKAGE_PIN M19 [get_ports {u1_tx}]; #data3-5
 set_property IOSTANDARD LVCMOS33 [get_ports {u1_tx}]
-set_property PACKAGE_PIN P20 [get_ports {u1_rx}]; #data3-11
+set_property PACKAGE_PIN N20 [get_ports {u0_tx}]; #data3-6
+set_property IOSTANDARD LVCMOS33 [get_ports {u0_tx}]
+set_property PACKAGE_PIN P18 [get_ports {u1_rx}]; #data3-7
 set_property IOSTANDARD LVCMOS33 [get_ports {u1_rx}]
+set_property PACKAGE_PIN M17 [get_ports {u0_rx}]; #data3-8
+set_property IOSTANDARD LVCMOS33 [get_ports {u0_rx}]
 
 set_property PACKAGE_PIN M20 [get_ports {scope_ch1}]; #data2-19
 set_property IOSTANDARD LVCMOS33 [get_ports {scope_ch1}]
diff --git a/fpga/hp_lcd_driver/fb_ram.vhdl b/fpga/hp_lcd_driver/fb_ram.vhdl
new file mode 100644
index 0000000..89c1a1a
--- /dev/null
+++ b/fpga/hp_lcd_driver/fb_ram.vhdl
@@ -0,0 +1,81 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+use work.all;
+
+entity fb_ram is
+  Port ( 
+    clka : in STD_LOGIC;
+    ena : in STD_LOGIC;
+    wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addra : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
+    clkb : in STD_LOGIC;
+    web : in STD_LOGIC_VECTOR ( 3 downto 0 );
+    addrb : in STD_LOGIC_VECTOR ( 15 downto 0 );
+    dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
+    doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
+  );
+end fb_ram;
+
+architecture Behavioural of fb_ram is
+type t_d is array (0 to 3) of std_logic_vector(2 downto 0);
+
+signal s_dina:t_d;
+signal s_dinb:t_d;
+signal s_douta:t_d;
+signal s_doutb:t_d;
+
+begin
+
+
+  g_fbram: for i in 0 to 3 generate
+
+    s_dina(i)(2) <= dina((8*i)+7);
+    s_dina(i)(1) <= dina((8*i)+4);
+    s_dina(i)(0) <= dina((8*i)+1);
+
+    douta((8*i)+7) <= s_douta(i)(2);
+    douta((8*i)+6) <= s_douta(i)(2);
+    douta((8*i)+5) <= s_douta(i)(2);
+    douta((8*i)+4) <= s_douta(i)(1);
+    douta((8*i)+3) <= s_douta(i)(1);
+    douta((8*i)+2) <= s_douta(i)(1);
+    douta((8*i)+1) <= s_douta(i)(0);
+    douta((8*i)+0) <= s_douta(i)(0);
+
+    s_dinb(i)(2) <= dinb((8*i)+7);
+    s_dinb(i)(1) <= dinb((8*i)+4);
+    s_dinb(i)(0) <= dinb((8*i)+1);
+
+    doutb((8*i)+7) <= s_doutb(i)(2);
+    doutb((8*i)+6) <= s_doutb(i)(2);
+    doutb((8*i)+5) <= s_doutb(i)(2);
+    doutb((8*i)+4) <= s_doutb(i)(1);
+    doutb((8*i)+3) <= s_doutb(i)(1);
+    doutb((8*i)+2) <= s_doutb(i)(1);
+    doutb((8*i)+1) <= s_doutb(i)(0);
+    doutb((8*i)+0) <= s_doutb(i)(0);
+
+
+ 
+    fb_ram_i : entity work.blk_mem_gen_1
+        port map (
+            clka  => clka,
+            ena   => ena,
+            wea   => wea(i),
+            addra => addra,
+            dina  => s_dina(i),
+            douta => s_douta(i),
+            clkb  => clkb,
+            web   => web(0),
+            addrb => addrb,
+            dinb  => s_dinb(i),
+            doutb => s_doutb(i)
+            );
+
+    end generate;
+
+
+end Behavioural;
diff --git a/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl b/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl
index 7005584..13d4573 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/axi_uart16550_0.tcl
@@ -5,6 +5,18 @@ source $source_dir/zynq7_config.tcl
 
 create_ip -name axi_uart16550 -vendor xilinx.com -library ip -version 2.0 -module_name axi_uart16550_0 -dir $ip_dir
 
+set_property -dict [ list \
+	CONFIG.C_EXTERNAL_XIN_CLK_HZ {25000000} \
+	CONFIG.C_HAS_EXTERNAL_RCLK {0} \
+	CONFIG.C_HAS_EXTERNAL_XIN {0} \
+	CONFIG.C_IS_A_16550 {16550} \
+	CONFIG.C_S_AXI_ACLK_FREQ_HZ {50000000} \
+	CONFIG.C_USE_MODEM_PORTS {1} \
+	CONFIG.C_USE_USER_PORTS {1} \
+	CONFIG.UART_BOARD_INTERFACE {Custom} \
+	] [get_ips axi_uart16550_0]
+
+
 generate_target all [get_ips]
 
 synth_ip [get_ips]
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index 0107700..8efbbb5 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -241,6 +241,12 @@ architecture arch of zynq7_wrapper is
     signal overlay_b    : std_logic_vector(7 downto 0);
 
 
+--	signal u0_t0 : std_logic;
+--	signal u0_t1 : std_logic;
+--	signal u1_t0 : std_logic;
+--	signal u1_t1 : std_logic;
+
+
 
 begin
 
@@ -617,6 +623,13 @@ begin
             );
 
 
+--        u0_t1 <= u0_rx and  u0_t0;
+--        u1_t1 <= u1_rx and  u1_t0;
+
+--	u1_tx <= u0_rx;
+--	u0_tx <= u1_rx;
+
+