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| author | root <root@new-fish.medaka.james.internal> | 2025-05-01 17:35:53 +0100 |
|---|---|---|
| committer | root <root@new-fish.medaka.james.internal> | 2025-05-01 17:35:53 +0100 |
| commit | b08cb4edeafd12fc9201c899d7b413a35e0c2b2c (patch) | |
| tree | 77500f3708a402c31f038c1766dbdbcff9da3311 /fpga/hp_lcd_driver | |
| parent | 01991b67d96900ab7cc2cf51987b4139de8bbe3d (diff) | |
| download | hp_instrument_lcds-b08cb4edeafd12fc9201c899d7b413a35e0c2b2c.tar.gz hp_instrument_lcds-b08cb4edeafd12fc9201c899d7b413a35e0c2b2c.tar.bz2 hp_instrument_lcds-b08cb4edeafd12fc9201c899d7b413a35e0c2b2c.zip | |
all working
Diffstat (limited to 'fpga/hp_lcd_driver')
| -rw-r--r-- | fpga/hp_lcd_driver/hp_lcd_driver.vhdl | 44 | ||||
| -rw-r--r-- | fpga/hp_lcd_driver/input_formatter.vhdl | 7 |
2 files changed, 38 insertions, 13 deletions
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl index d553043..d45b176 100644 --- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl +++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl @@ -3,10 +3,18 @@ use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; use work.all; +-- on the cyclone iv +-- i_clk/4 = 19.676158 +-- the scope's pixel clock is 19.66080 +-- (p-0.25)*19.66080 = p * 19.676158 +--p=1/[4*(1-(19.676158/19.66080))]=320.04 + + entity hp_lcd_driver is generic (video_width : natural := 2; addr_width : natural := 18; - phase_slip : natural := 160; + phase_slip : natural := 320; + i_clk_multiple : natural := 4; target : string := "spartan6"); port (clk_50m : in std_logic; sys_rst_n : in std_logic; @@ -97,9 +105,9 @@ begin epk <= '1'; if pa = 0 then pa <= phase_slip; - ic <= 4; + ic <= i_clk_multiple; else - ic <= 3; + ic <= i_clk_multiple-1; pa <= pa -1; end if; else @@ -119,9 +127,9 @@ begin generic map( video_width => video_width, addr_width => addr_width, - clk_multiple => 4, - phase => 3, - h_front_porch => 209, + clk_multiple => i_clk_multiple, + phase => 1, + h_front_porch => 210, h_active => 592, v_front_porch => 1, v_active => 384, @@ -204,16 +212,38 @@ begin generic map ( target => target, addr_width => addr_width, +-- h_active => 384, +-- h_sync_start => 400, +-- h_sync_end => 440, +-- h_total => 640, +-- v_active => 592, +-- v_sync_start => 593, +-- v_sync_end => 596, +-- v_total => 613, +-- h_stride => 1, +-- v_stride => 384 + h_active => 384, h_sync_start => 400, h_sync_end => 440, - h_total => 640, + h_total => 660, v_active => 592, v_sync_start => 593, v_sync_end => 596, v_total => 613, h_stride => 1, v_stride => 384 + +-- h_active => 800, +-- h_sync_start => 832, +-- h_sync_end => 912, +-- h_total => 1024, +-- v_active => 600, +-- v_sync_start => 601, +-- v_sync_end => 604, +-- v_total => 622, +-- h_stride => 1, +-- v_stride => 384 ) port map( clk_locked => clk_locked, diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl index 82c17f6..12037ef 100644 --- a/fpga/hp_lcd_driver/input_formatter.vhdl +++ b/fpga/hp_lcd_driver/input_formatter.vhdl @@ -2,11 +2,6 @@ library ieee; use ieee.std_logic_1164.all; use IEEE.NUMERIC_STD.all; --- i_clk is 78.704625 --- the scope's pixel clock is 19.660819 --- ratio is 4.003120 --- 1/0.003120 is 320 - entity input_formatter is @@ -114,7 +109,7 @@ begin h_div <= clk_multiple; else phase_accum <= phase_accum-1; - h_div <= clk_multiple -1; + h_div <= clk_multiple-1; end if; else if wren = '1' then |