working

7 files changed, 111 insertions, 27 deletions

diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index e1625ba..d553043 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -6,7 +6,7 @@ use work.all;
 entity hp_lcd_driver is
     generic (video_width : natural := 2;
              addr_width  : natural := 18;
-             phase_slip  : natural := 320;
+             phase_slip  : natural := 160;
              target      : string  := "spartan6");
     port (clk_50m   : in  std_logic;
           sys_rst_n : in  std_logic;
@@ -58,6 +58,10 @@ architecture Behavioral of hp_lcd_driver is
     signal ic  : natural;
 
 
+    signal h:natural;
+    signal v:natural;
+
+
 
 begin
 
@@ -117,11 +121,11 @@ begin
             addr_width    => addr_width,
             clk_multiple  => 4,
             phase         => 3,
-            h_front_porch => 208,
+            h_front_porch => 209,
             h_active      => 592,
-            v_front_porch => 2,
+            v_front_porch => 1,
             v_active      => 384,
-            frame_start   => 380,
+            frame_start   => 383,
             h_stride      => 384,
             v_stride      => 262143,
             phase_slip    => phase_slip
@@ -134,10 +138,38 @@ begin
             vsync_in  => vsync_in,
 
             video_out => wr_data,
-            addr_out  => wr_addr,
-            wren_out  => wr_en);
-
-
+            addr_out  =>wr_addr,
+            wren_out  =>wr_en
+);
+
+--
+--    process (i_clk) begin
+--	if sys_rst_n='0' then
+--		h<=0;
+--		v<=0;
+--		wr_addr <=(others =>'0');
+--	elsif rising_edge(i_clk) then
+--		if h /= 383 then
+--			h<=h+1;
+--         	        wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
+--		else
+--			h<=0;
+--			if v /= 591 then
+--			v<=v+1;
+--         	        wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
+--			else
+--			v<=0;
+--			wr_addr <=(others =>'0');
+--			end if;
+--		end if;
+--	end if;
+--     end process;
+--
+--    wr_en <= '1';
+--	
+--    wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591)
+--		else "00";
+--
     vram0 : entity work.vram
         generic map (
             video_width => video_width,
@@ -175,7 +207,7 @@ begin
             h_active     => 384,
             h_sync_start => 400,
             h_sync_end   => 440,
-            h_total      => 620,
+            h_total      => 640,
             v_active     => 592,
             v_sync_start => 593,
             v_sync_end   => 596,
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
index 9c04493..82c17f6 100644
--- a/fpga/hp_lcd_driver/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -132,10 +132,11 @@ begin
     wren_out <= wren;
 
 
-    h_grid <= '1' when (h_active_counter mod 8) = 0
+    h_grid <= '1' when ((h_active_counter mod 16) = (h_active mod 16)) or (h_Active_counter=1)
+--    h_grid <= '1' when (h_active_counter=h_active) or (h_active_counter=h_active-2)
               else '0';
 
-    v_grid <= '1' when (v_active_counter mod 8) = 0
+    v_grid <= '1' when ((v_active_counter mod 16) = (v_active mod 16)) or (v_active_counter=1)
               else '0';
 
 
diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl
index e9a7549..9355a93 100644
--- a/fpga/hp_lcd_driver/input_stage.vhdl
+++ b/fpga/hp_lcd_driver/input_stage.vhdl
@@ -56,7 +56,7 @@ begin
 
     video_sync_for : for b in 0 to video_width -1 generate
         sync : entity work.synchronizer
-            generic map(stages => sync_stages + debounce_stages)
+            generic map(stages => sync_stages + debounce_stages +1)
             port map (
                 clk => clk,
                 i   => video_in(b),
@@ -135,6 +135,9 @@ begin
 
     video_out <= s_video;
 
+--video_out(0) <= s_video(0);
+--video_out(1) <= h_grid or v_grid;
+
     --video_out(0) <= h_grid;
     --video_out(1) <= v_grid;
 
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
index aafce2c..b99f59e 100644
--- a/fpga/hp_lcd_driver/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -86,13 +86,16 @@ begin
             row_addr <= (others => '0');
             addr     <= (others => '0');
             blank    <= '1';
+	    vblank <='1';
             vsync    <= '0';
             hsync    <= '0';
         elsif rising_edge(clk) then
 
             if h = 0 then
                 if v = 0 then
-                    row_addr <= (others => '0');
+                    --row_addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
+                    row_addr <= std_logic_vector(to_unsigned(v_stride,row_addr'length));
+                    --addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
                     addr     <= (others => '0');
                     blank    <= '0';
                     vblank   <= '0';
@@ -116,13 +119,15 @@ begin
             else
                 addr <= std_logic_vector(unsigned(addr)+h_stride);
             end if;
-        end if;
+	end if;
     end process;
 
-    h_grid <= '1' when (h mod 8) = 0
+--    h_grid <= '1' when (h mod 8) = 0
+    h_grid <= '1' when (h =0) or (h=(h_active-1))
               else '0';
 
-    v_grid <= '1' when (v mod 8) = 0
+--    v_grid <= '1' when (v mod 8) = 0
+    v_grid <= '1' when (v =0) or (v=(v_active-1))
               else '0';
 
 
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index 08dcfdd..d9addbf 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -61,10 +61,14 @@ architecture beh of output_stage is
     signal d_vsync_in : std_logic;
 
     signal blank : std_logic;
-
     signal hsync : std_logic;
     signal vsync : std_logic;
 
+    signal blank_d : std_logic;
+    signal hsync_d : std_logic;
+    signal vsync_d : std_logic;
+    signal grid_d : std_logic;
+
     signal addr : std_logic_vector(addr_width - 1 downto 0);
 
     signal r : std_logic_vector(7 downto 0);
@@ -128,20 +132,59 @@ begin
 
     addr_out <= addr;
 
+--    dg : entity work.delay
+--        generic map(stages => 1)
+--        port map (
+--            clk => clk,
+--            i   => h_grid or v_grid,
+--            o   => grid_d
+--            );
 
     r <= r_in;
     g <= g_in;
     b <= b_in;
 
+--    b<=x"00" when grid_d='0'
+--          else x"ff";
 
 --    r<=x"00" when h_grid='0'
 --          else x"ff";
 
---    g<=x"00" when v_grid='0'
+--    b<=x"00" when v_grid='0' and h_grid='0'
 --          else x"ff";
 
+--
+--    dh : entity work.delay
+--        generic map(stages => 10)
+--        port map (
+--            clk => clk,
+--            i   => hsync,
+--            o   => hsync_d
+--            );
+--
+--
+--
+--    dv : entity work.delay
+--        generic map(stages => 10)
+--        port map (
+--            clk => clk,
+--            i   => vsync,
+--            o   => vsync_d
+--            );
+--
+--
+--
+    dn : entity work.delay
+        generic map(stages => 1)
+        port map (
+            clk => clk,
+            i   => blank,
+            o   => blank_d
+            );
 
 
+hsync_d <=hsync;
+vsync_d <=vsync;
 
 
     analog : entity work.output_analog
@@ -150,9 +193,9 @@ begin
 
             clk => clk,
 
-            hsync_in => hsync,
-            vsync_in => vsync,
-            blank_in => blank,
+            hsync_in => hsync_d,
+            vsync_in => vsync_d,
+            blank_in => blank_d,
             r_in     => g(7),
             g_in     => r(7),
             b_in     => b(7),
@@ -172,9 +215,9 @@ begin
         r_in  => r,
         g_in  => g,
         b_in  => b,
-        hsync => hsync,
-        vsync => vsync,
-        blank => blank,
+        hsync => hsync_d,
+        vsync => vsync_d,
+        blank => blank_d,
 
         r_p10 => r_p10,
         g_p10 => g_p10,
diff --git a/fpga/hp_lcd_driver/smh-ac415.mk b/fpga/hp_lcd_driver/smh-ac415.mk
index 0d37eb7..7c2d649 100644
--- a/fpga/hp_lcd_driver/smh-ac415.mk
+++ b/fpga/hp_lcd_driver/smh-ac415.mk
@@ -8,7 +8,7 @@ BUILD=build_${BOARD}
 OF=output_files
 
 PROJECT = hp_lcd_driver
-VSRCS =synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl  output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
+VSRCS =delay.vhdl synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl tmds_encoder.vhdl tmds_encode.vhdl tmds_phy_cyclone4.vhdl tmds_output_cyclone4.vhdl  output_stage.vhdl clkgen_cyclone4.vhdl vram_cyclone4.vhdl hp_lcd_driver.vhdl
 IPS= vram_cyclone4_impl.vhdl  clkgen_cyclone4_a_impl.vhdl clkgen_cyclone4_b_impl.vhdl
 
 DESIGN_NAME=${TOP}
diff --git a/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl b/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl
index aea5b80..2c50527 100644
--- a/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl
+++ b/fpga/hp_lcd_driver/vram_cyclone4_impl.vhdl
@@ -103,8 +103,8 @@ BEGIN
 		clock_enable_output_b => "BYPASS",
 		intended_device_family => "Cyclone IV E",
 		lpm_type => "altsyncram",
-		numwords_a => 228096,
-		numwords_b => 228096,
+		numwords_a => 245760,
+		numwords_b => 245760,
 		operation_mode => "DUAL_PORT",
 		outdata_aclr_b => "NONE",
 		outdata_reg_b => "UNREGISTERED",