tidyingup

9 files changed, 82 insertions, 51 deletions

diff --git a/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl b/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
index 3309d00..4c67907 100644
--- a/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_cyclone4.vhdl
@@ -16,17 +16,17 @@ entity clkgen is
 end clkgen;
 architecture Behavioural of clkgen is
 
-    signal clkfbout   : std_logic;
-    signal clk_120m   : std_logic;
+    signal clkfbout    : std_logic;
+    signal clk_120m    : std_logic;
     signal clk_78_642m : std_logic;
-    signal clk_48m    : std_logic;
-    signal clk_24m    : std_logic;
-    signal pll_locked : std_logic;
+    signal clk_48m     : std_logic;
+    signal clk_24m     : std_logic;
+    signal pll_locked  : std_logic;
 
     signal reset : std_logic;
 begin
 
-     clkgen_a : entity work.clkgen_cyclone4_a_impl
+    clkgen_a : entity work.clkgen_cyclone4_a_impl
         port map (
             areset => not sys_rst_n,
             inclk0 => clk_in,
diff --git a/fpga/hp_lcd_driver/delay.vhdl b/fpga/hp_lcd_driver/delay.vhdl
index 2e777b6..66c5c5d 100644
--- a/fpga/hp_lcd_driver/delay.vhdl
+++ b/fpga/hp_lcd_driver/delay.vhdl
@@ -9,7 +9,7 @@ entity delay is
 end delay;
 
 architecture Behavioral of delay is
-    signal flipflops                 : std_logic_vector(stages-1 downto 0) := (others => '0');
+    signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
 begin
 
     o <= flipflops(flipflops'high);
diff --git a/fpga/hp_lcd_driver/ep4ce15-bis.cfg b/fpga/hp_lcd_driver/ep4ce15-bis.cfg
new file mode 100644
index 0000000..77e4751
--- /dev/null
+++ b/fpga/hp_lcd_driver/ep4ce15-bis.cfg
@@ -0,0 +1,11 @@
+source [find fpga/altera-cycloneiv.cfg]
+
+#pld create cycloneiv.pld intel -chain-position cycloneiii.tap -family cycloneiii
+
+init
+#scan_chain
+#svf -tap $CHIPNAME.tap ./build_ep4ce15/hp_lcd_driver.svf
+#pld intel build_ep4ce15/hp_lcd_driver.rbf
+pld load cycloneiv.pld build_ep4ce15/hp_lcd_driver.rbf
+shutdown
+quit
diff --git a/fpga/hp_lcd_driver/g b/fpga/hp_lcd_driver/g
new file mode 100755
index 0000000..1ee944e
--- /dev/null
+++ b/fpga/hp_lcd_driver/g
@@ -0,0 +1,5 @@
+#!/bin/bash
+set -e
+make smh-ac415
+rsync -varP -e ssh ./ 10.16.66.111:${PWD}/ 
+ssh 10.16.66.111 "cd ${PWD} && /root/prog"
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index d45b176..98714e4 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -11,11 +11,11 @@ use work.all;
 
 
 entity hp_lcd_driver is
-    generic (video_width : natural := 2;
-             addr_width  : natural := 18;
-             phase_slip  : natural := 320;
-	     i_clk_multiple : natural := 4;
-             target      : string  := "spartan6");
+    generic (video_width    : natural := 2;
+             addr_width     : natural := 18;
+             phase_slip     : natural := 320;
+             i_clk_multiple : natural := 4;
+             target         : string  := "spartan6");
     port (clk_50m   : in  std_logic;
           sys_rst_n : in  std_logic;
           video     : in  std_logic_vector(video_width-1 downto 0);
@@ -66,8 +66,8 @@ architecture Behavioral of hp_lcd_driver is
     signal ic  : natural;
 
 
-    signal h:natural;
-    signal v:natural;
+    signal h : natural;
+    signal v : natural;
 
 
 
@@ -146,37 +146,37 @@ begin
             vsync_in  => vsync_in,
 
             video_out => wr_data,
-            addr_out  =>wr_addr,
-            wren_out  =>wr_en
-);
+            addr_out  => wr_addr,
+            wren_out  => wr_en
+            );
 
 --
 --    process (i_clk) begin
---	if sys_rst_n='0' then
---		h<=0;
---		v<=0;
---		wr_addr <=(others =>'0');
---	elsif rising_edge(i_clk) then
---		if h /= 383 then
---			h<=h+1;
---         	        wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
---		else
---			h<=0;
---			if v /= 591 then
---			v<=v+1;
---         	        wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
---			else
---			v<=0;
---			wr_addr <=(others =>'0');
---			end if;
---		end if;
---	end if;
+--      if sys_rst_n='0' then
+--              h<=0;
+--              v<=0;
+--              wr_addr <=(others =>'0');
+--      elsif rising_edge(i_clk) then
+--              if h /= 383 then
+--                      h<=h+1;
+--                      wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
+--              else
+--                      h<=0;
+--                      if v /= 591 then
+--                      v<=v+1;
+--                      wr_addr <= std_logic_vector(unsigned(wr_addr)+1);
+--                      else
+--                      v<=0;
+--                      wr_addr <=(others =>'0');
+--                      end if;
+--              end if;
+--      end if;
 --     end process;
 --
 --    wr_en <= '1';
---	
+--      
 --    wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591)
---		else "00";
+--              else "00";
 --
     vram0 : entity work.vram
         generic map (
@@ -210,8 +210,8 @@ begin
 --  Modeline "384x592_80.00"  25.40  384 408 448 512  592 593 596 620  -HSync +Vsync
 
         generic map (
-            target       => target,
-            addr_width   => addr_width,
+            target     => target,
+            addr_width => addr_width,
 --            h_active     => 384,
 --            h_sync_start => 400,
 --            h_sync_end   => 440,
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
index 12037ef..f3bd434 100644
--- a/fpga/hp_lcd_driver/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -127,11 +127,11 @@ begin
     wren_out <= wren;
 
 
-    h_grid <= '1' when ((h_active_counter mod 16) = (h_active mod 16)) or (h_Active_counter=1)
+    h_grid <= '1' when ((h_active_counter mod 16) = (h_active mod 16)) or (h_Active_counter = 1)
 --    h_grid <= '1' when (h_active_counter=h_active) or (h_active_counter=h_active-2)
-              else '0';
+else '0';
 
-    v_grid <= '1' when ((v_active_counter mod 16) = (v_active mod 16)) or (v_active_counter=1)
+    v_grid <= '1' when ((v_active_counter mod 16) = (v_active mod 16)) or (v_active_counter = 1)
               else '0';
 
 
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
index b99f59e..d11a8a1 100644
--- a/fpga/hp_lcd_driver/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -86,7 +86,7 @@ begin
             row_addr <= (others => '0');
             addr     <= (others => '0');
             blank    <= '1';
-	    vblank <='1';
+            vblank   <= '1';
             vsync    <= '0';
             hsync    <= '0';
         elsif rising_edge(clk) then
@@ -94,7 +94,7 @@ begin
             if h = 0 then
                 if v = 0 then
                     --row_addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
-                    row_addr <= std_logic_vector(to_unsigned(v_stride,row_addr'length));
+                    row_addr <= std_logic_vector(to_unsigned(v_stride, row_addr'length));
                     --addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
                     addr     <= (others => '0');
                     blank    <= '0';
@@ -119,15 +119,15 @@ begin
             else
                 addr <= std_logic_vector(unsigned(addr)+h_stride);
             end if;
-	end if;
+        end if;
     end process;
 
 --    h_grid <= '1' when (h mod 8) = 0
-    h_grid <= '1' when (h =0) or (h=(h_active-1))
+    h_grid <= '1' when (h = 0) or (h = (h_active-1))
               else '0';
 
 --    v_grid <= '1' when (v mod 8) = 0
-    v_grid <= '1' when (v =0) or (v=(v_active-1))
+    v_grid <= '1' when (v = 0) or (v = (v_active-1))
               else '0';
 
 
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index d9addbf..984c7c5 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -67,7 +67,7 @@ architecture beh of output_stage is
     signal blank_d : std_logic;
     signal hsync_d : std_logic;
     signal vsync_d : std_logic;
-    signal grid_d : std_logic;
+    signal grid_d  : std_logic;
 
     signal addr : std_logic_vector(addr_width - 1 downto 0);
 
@@ -183,8 +183,8 @@ begin
             );
 
 
-hsync_d <=hsync;
-vsync_d <=vsync;
+    hsync_d <= hsync;
+    vsync_d <= vsync;
 
 
     analog : entity work.output_analog
diff --git a/fpga/hp_lcd_driver/prog-bis b/fpga/hp_lcd_driver/prog-bis
new file mode 100755
index 0000000..a3677a6
--- /dev/null
+++ b/fpga/hp_lcd_driver/prog-bis
@@ -0,0 +1,15 @@
+#!/bin/bash
+
+B=hp_lcd_driver
+SOF=build_ep4ce15/output_files/$B.sof
+SVF=build_ep4ce15/$B.svf
+RBF=build_ep4ce15/$B.rbf
+#run_quartus quartus_cpf -c -q 1MHZ -g 3.3 -n p ${SOF} ${SVF}
+run_quartus quartus_cpf -c  ${SOF} ${RBF}
+
+#OPENOCD="/root/projects/hp_instrument_lcds/fpga/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f fpga/altera-cycloneiv.cfg"
+#${OPENOCD} -c "init; pld load cycloneiv.pld vga_colorbar.rbf; shutdown; quit"
+
+OPENOCD="/root/projects/hp_instrument_lcds/fpga/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f ep4ce15-bis.cfg"
+${OPENOCD} 
+