Wednesday's progress - happy working a7, changes to bt475 hat

15 files changed, 219 insertions, 110 deletions

diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index e9f1df7..458951d 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,7 +1,10 @@
 TARGETS= rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
 #fish:smh-ac415
 
-default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
+better_default: build_rando_a7/hp_lcd_driver.svf
+	./prog_a7
+
+default: ${TARGETS:%=build_%/hp_lcd_driver.svf} 
 
 
 
@@ -9,8 +12,6 @@ smh-ac415: build_smh-ac415/hp_lcd_driver.svf
 spartan6: build_spartan6/hp_lcd_driver.svf
 rando_a7: build_rando_a7/out/hp_lcd_driver.bit
 
-
-
 build_%/hp_lcd_driver.svf: dummy
 	${MAKE} -f ${@:build_%/hp_lcd_driver.svf=%}.mk
 
diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
index 578468c..8c83e78 100644
--- a/fpga/hp_lcd_driver/artix7.mk
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -7,6 +7,7 @@ IP= \
 
 
 BIT=${BUILD}/out/hp_lcd_driver.bit
+BIN=${BUILD}/out/hp_lcd_driver.bin
 
 IP_STAMP=${IP:artix7_ip/%.tcl=${BUILD}/ip/%/stamp}
 SRCS= ${IP} \
@@ -35,11 +36,12 @@ SRCS= ${IP} \
 
 OPENOCD=openocd -f openocd/${BOARD}.cfg
 
-default:  ${BUILD}/build.stamp
+default:  ${BUILD}/build.stamp 
 
 ${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
 	mkdir -p ${BUILD}
 	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch  -source ../artix7_hp_lcd_driver.tcl)
+	scripts/xilinx_bit_to_bin.pl ${BIT} ${BIN}
 	touch $@
 
 ${BUILD}/ip/%/stamp:artix7_ip/%.tcl
diff --git a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
index 684e493..3859382 100644
--- a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
@@ -24,6 +24,7 @@ read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../de
 
 set generics {}
 append generics { } "video_width=$video_width"
+append generics { } "input_video_width=$input_video_width"
 append generics { } "BOARD=\"$board\""
 append generics { } "use_pclk=$use_pclk"
 
diff --git a/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl b/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl
index a49c8f2..dda6633 100644
--- a/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl
+++ b/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl
@@ -9,12 +9,12 @@ set_property -dict [list \
 	CONFIG.CLKOUT2_USED {true} \
 	CONFIG.CLKOUT3_USED {true} \
 	CONFIG.CLKOUT4_USED {true} \
-	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {240} \
-	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80} \
-	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {48} \
-	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {24} \
+	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {260} \
+	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {86.667} \
+	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {52} \
+	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {26} \
 	CONFIG.CLKIN1_JITTER_PS {200.0} \
-	CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \
+	CONFIG.MMCM_CLKFBOUT_MULT_F {26.000} \
 	CONFIG.MMCM_CLKIN1_PERIOD {20.000} \
 	CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
 	CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
diff --git a/fpga/hp_lcd_driver/flash_a7 b/fpga/hp_lcd_driver/flash_a7
new file mode 100755
index 0000000..caf46ec
--- /dev/null
+++ b/fpga/hp_lcd_driver/flash_a7
@@ -0,0 +1,5 @@
+#!/bin/bash
+BIN=./build_rando_a7/out/hp_lcd_driver.bit
+SPIBIT=../../openocd/bscan_spi/bscan_spi_xc7a35t.bit
+../../openocd/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f cpld/xilinx-xc7.cfg -f cpld/jtagspi.cfg  -c init -c "jtagspi_init xc7.pld ${SPIBIT}; jtagspi_program $BIN 0" -c shutdown
+
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index 95a38a1..94199b9 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -11,7 +11,8 @@ use work.all;
 
 
 entity hp_lcd_driver is
-    generic (video_width    : natural := 2;
+    generic (input_video_width    : natural := 2;
+	     video_width : natural :=2;
              addr_width     : natural := 18;
              phase_slip     : natural := 320;
              i_clk_multiple : natural := 4;
@@ -19,7 +20,7 @@ entity hp_lcd_driver is
              target         : string  := "artix7");
     port (clk_50m   : in  std_logic;
           sys_rst_n : in  std_logic;
-          video     : in  std_logic_vector(video_width -1 downto 0);
+          video     : in  std_logic_vector(input_video_width -1 downto 0);
           hsync_in  : in  std_logic;
           vsync_in  : in  std_logic;
           pclk_in   : in  std_logic;
@@ -44,8 +45,10 @@ end hp_lcd_driver;
 
 architecture Behavioral of hp_lcd_driver is
 
+    signal video_lut : std_logic_vector (video_width-1 downto 0);
     signal wr_addr : std_logic_vector(addr_width-1 downto 0);
     signal wr_data : std_logic_vector(video_width-1 downto 0);
+    signal wr_data_b : std_logic_vector(video_width-1 downto 0);
     signal wr_en   : std_logic;
 
     signal rd_addr : std_logic_vector(addr_width-1 downto 0);
@@ -98,6 +101,16 @@ begin
             );
 
 
+video_lut <= "1111" when video(0)='1' else
+	     "1011" when video(1)='1' else
+	     "1100" when video(2)='1' else
+	     "1010" when video(3)='1' else
+	     "0011" when video(4)='1' else
+	     "1110" when video(5)='1' else
+	     "1001" when video(6)='1' else
+	     "1101" when video(7)='1' else
+	     "0000";
+
 
     process (i_clk, sys_rst_n)
     begin
@@ -136,7 +149,7 @@ begin
             clk_multiple  => i_clk_multiple,
 -- HP54502A
 --            phase         => 1,
---            h_front_porch => 210,
+--            h_front_porch => 200,
 --            h_active      => 592,
 --            v_front_porch => 1,
 --            v_active      => 384,
@@ -145,7 +158,7 @@ begin
 --            v_stride      => 262143,
 -- HP54522A
             phase         => 1,
-            h_front_porch => 213,
+            h_front_porch => 190,
             h_active      => 640,
             v_front_porch => 22,
             v_active      => 384,
@@ -158,7 +171,7 @@ begin
         port map (
             sys_rst_n => sys_rst_n,
             clk       => i_clk,
-            video_in  => video,
+            video_in  => video_lut,
             pclk_in   => pclk_in,
             hsync_in  => not hsync_in,
             vsync_in  => not vsync_in,
@@ -196,6 +209,7 @@ begin
 --    wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591)
 --              else "00";
 --
+
     vram0 : entity work.vram
         generic map (
             video_width => video_width,
@@ -216,9 +230,24 @@ begin
 --   r<=x"00";
 --   b<=x"00";
 
-    r <= rd_data(1 downto 0) & "000000";
-    g <= rd_data(3 downto 2) & "000000";
-    b <= rd_data(5 downto 4) & "000000";
+
+
+
+    r<=x"ff" when rd_data(0)='1' else
+	 x"00";
+
+--    r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
+--	 x"80" when rd_data(0)='1' else
+--	 x"00";
+
+    g<=x"ff" when rd_data(1)='1' and rd_data(3)='1' else
+	 x"80" when rd_data(1)='1' else
+	 x"00";
+    b<=x"ff" when rd_data(2)='1' and rd_data(3)='1' else
+	 x"80" when rd_data(2)='1' else
+	 x"00";
+
+    
 
 --"ff" when rd_data(1) = '1' else
 --         x"80" when rd_data(0) = '1' else
@@ -261,7 +290,7 @@ begin
 -- HP54522A
             h_active     => 384,
             h_sync_start => 400,
-            h_sync_end   => 440,
+            h_sync_end   => 456,
             h_total      => 660,
 --            h_active     => 417,
 --            h_sync_start => 440,
@@ -294,7 +323,7 @@ begin
             clk_x2     => o_clk_x2,
             clk_phy    => o_clk_phy,
             sys_rst_n  => sys_rst_n,
-            vsync_in   => vsync_in,
+            vsync_in   => not vsync_in,
             r_in       => r,
             g_in       => g,
             b_in       => b,
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
index 35916f5..f8b27c2 100644
--- a/fpga/hp_lcd_driver/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -72,7 +72,7 @@ begin
         port map(
             clk => clk,
             sig => pclk,
-            e   => pclk_ne,
+            ne  => pclk_ne,
             pe  => pclk_pe);
 
 
@@ -131,7 +131,7 @@ begin
                         wren  <= '0';
                     end if;
                 else
-		    wren <= pclk_pe;
+		    wren <= pclk_ne;
                 end if;
 
                 if wren = '1' then
diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl
index c124a59..1316b6e 100644
--- a/fpga/hp_lcd_driver/input_stage.vhdl
+++ b/fpga/hp_lcd_driver/input_stage.vhdl
@@ -71,7 +71,7 @@ begin
 
 
     pclk_sync : entity work.synchronizer
-        generic map(stages => sync_stages)
+        generic map(stages => sync_stages + debounce_stages+1)
         port map (
             clk => clk,
             i   => pclk_in,
@@ -95,13 +95,6 @@ begin
             );
 
 
-    pclk_debounce : entity work.debounce
-        generic map(stages => debounce_stages)
-        port map(
-            clk => clk,
-            i   => s_pclk,
-            o   => d_pclk);
-
     hsync_debounce : entity work.debounce
         generic map(stages => debounce_stages)
         port map(
@@ -135,7 +128,7 @@ begin
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
-            pclk      => d_pclk,
+            pclk      => s_pclk,
             hsync     => d_hsync,
             vsync     => d_vsync,
             addr_out  => addr,
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
index 558c222..1f9e89f 100644
--- a/fpga/hp_lcd_driver/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -26,8 +26,7 @@ entity output_formatter is
         blank_out : out std_logic;
         vsync_out : out std_logic;
         hsync_out : out std_logic;
-        h_grid    : out std_logic;
-        v_grid    : out std_logic
+        grid_out  : out std_logic
         );
 end output_formatter;
 
@@ -42,11 +41,11 @@ architecture beh of output_formatter is
     signal h : natural;
     signal v : natural;
 
-
     signal blank  : std_logic;
     signal vblank : std_logic;
     signal vsync  : std_logic;
     signal hsync  : std_logic;
+    signal grid  : std_logic;
 
 
 begin
@@ -71,7 +70,7 @@ begin
                 if v /= (v_total-1) then
                     v <= v+1;
                     h <= 0;
-                else                    --if vsync_in_ne = '1' then
+                else  --if vsync_in_ne = '1' then -- JMM if we synchronise the vsyncs then the display goes to sleep
                     h <= 0;
                     v <= 0;
                 end if;
@@ -89,17 +88,16 @@ begin
             vblank   <= '1';
             vsync    <= '0';
             hsync    <= '0';
+	    grid <='0';
         elsif rising_edge(clk) then
-
             if h = 0 then
                 if v = 0 then
-                    --row_addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
                     row_addr <= std_logic_vector(to_unsigned(v_stride, row_addr'length));
-                    --addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
                     addr     <= (others => '0');
+                    --addr     <= std_logic_vector(to_unsigned(h_stride, addr'length));
                     blank    <= '0';
                     vblank   <= '0';
-                elsif v = v_active then
+                elsif v = v_active  then
                     vblank <= '1';
                 elsif v = v_sync_start then
                     vsync <= '1';
@@ -108,7 +106,8 @@ begin
                 else
                     blank    <= vblank;
                     row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
-                    addr     <= row_addr;
+		    addr <= row_addr;
+                    --addr     <= std_logic_vector(unsigned(row_addr)+h_stride);
                 end if;
             elsif h = h_active then
                 blank <= '1';
@@ -119,22 +118,27 @@ begin
             else
                 addr <= std_logic_vector(unsigned(addr)+h_stride);
             end if;
+
+    grid <= '1' when h  = 0 else
+	'1' when h=10 else
+	'1' when h=h_active-11 else
+	'1' when h=h_active-1 else
+        '1' when v=0 else
+	'1' when v=10 else
+	'1' when v=v_active-11 else
+	'1' when v=v_active-1 else
+	'0';
+
         end if;
     end process;
 
-    h_grid <= '1' when (h mod 32) = 0
---    h_grid <= '1' when (h = 0) or (h = (h_active-1))
-else '0';
-
-    v_grid <= '1' when (v mod 32) = 0
---    v_grid <= '1' when (v = 0) or (v = (v_active-1))
-else '0';
 
 
     addr_out  <= addr;
     blank_out <= blank;
     hsync_out <= hsync;
     vsync_out <= vsync;
+    grid_out <= grid;
 
 end beh;
 
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index 56f4ae4..b43dc50 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -75,8 +75,7 @@ architecture beh of output_stage is
     signal g : std_logic_vector(7 downto 0);
     signal b : std_logic_vector(7 downto 0);
 
-    signal h_grid : std_logic;
-    signal v_grid : std_logic;
+    signal grid : std_logic;
 
     signal r_p10 : std_logic_vector(9 downto 0);
     signal g_p10 : std_logic_vector(9 downto 0);
@@ -125,59 +124,49 @@ begin
             blank_out => blank,
             vsync_out => vsync,
             hsync_out => hsync,
-            h_grid    => h_grid,
-            v_grid    => v_grid
+            grid_out    => grid
             );
 
 
     addr_out <= addr;
 
---    dg : entity work.delay
---        generic map(stages => 1)
---        port map (
---            clk => clk,
---            i   => h_grid or v_grid,
---            o   => grid_d
---            );
+    dg : entity work.delay
+        generic map(stages => 2)
+        port map (
+            clk => clk,
+            i   => grid, 
+            o   => grid_d
+            );
 
-    r <= r_in;
+    r <=  r_in;
     g <= g_in;
     b <= b_in;
 
 
 
---    b<=x"00" when v_grid='0'
---          else x"ff";
-
---    r<=x"00" when h_grid='0'
---          else x"ff";
-
---    b<=x"00" when v_grid='0' and h_grid='0'
---          else x"ff";
-
---
---    dh : entity work.delay
---        generic map(stages => 10)
---        port map (
---            clk => clk,
---            i   => hsync,
---            o   => hsync_d
---            );
---
---
---
---    dv : entity work.delay
---        generic map(stages => 10)
---        port map (
---            clk => clk,
---            i   => vsync,
---            o   => vsync_d
---            );
---
---
---
-    dn : entity work.delay
-        generic map(stages => 1)
+
+    dh : entity work.delay
+        generic map(stages => 2)
+        port map (
+            clk => clk,
+            i   => hsync,
+            o   => hsync_d
+            );
+
+
+
+    dv : entity work.delay
+        generic map(stages => 2)
+        port map (
+            clk => clk,
+            i   => vsync,
+            o   => vsync_d
+            );
+
+
+
+    db : entity work.delay
+        generic map(stages => 2)
         port map (
             clk => clk,
             i   => blank,
@@ -185,9 +174,6 @@ begin
             );
 
 
-    hsync_d <= hsync;
-    vsync_d <= vsync;
-
 
     analog : entity work.output_analog
         port map(
diff --git a/fpga/hp_lcd_driver/prog_a7 b/fpga/hp_lcd_driver/prog_a7
index c10ee8f..6421562 100755
--- a/fpga/hp_lcd_driver/prog_a7
+++ b/fpga/hp_lcd_driver/prog_a7
@@ -1,4 +1,4 @@
 #!/bin/bash
-BIT=./build-rando_a7/out/hp_lcd_driver.bit
+BIT=./build_rando_a7/out/hp_lcd_driver.bit
 ../../openocd/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f cpld/xilinx-xc7.cfg -c init -c "pld load xc7.pld $BIT" -c shutdown
 
diff --git a/fpga/hp_lcd_driver/rando_a7.tcl b/fpga/hp_lcd_driver/rando_a7.tcl
index cfaa74d..cb14260 100644
--- a/fpga/hp_lcd_driver/rando_a7.tcl
+++ b/fpga/hp_lcd_driver/rando_a7.tcl
@@ -2,4 +2,5 @@
 set part_num "xc7a35tfgg484-2"
 set normal_xdc "../rando_a7.xdc"
 set use_pclk 1
-set video_width 6
+set input_video_width 8
+set video_width 4
diff --git a/fpga/hp_lcd_driver/rando_a7.xdc b/fpga/hp_lcd_driver/rando_a7.xdc
index 04b2cac..3f3c24d 100644
--- a/fpga/hp_lcd_driver/rando_a7.xdc
+++ b/fpga/hp_lcd_driver/rando_a7.xdc
@@ -9,12 +9,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led}]
 #set_property PACKAGE_PIN T1 [get_ports {led_1}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
 
-set_property PACKAGE_PIN R3 [get_ports {hdmi_r_p}]
-set_property PACKAGE_PIN R2 [get_ports {hdmi_r_n}]
+set_property PACKAGE_PIN U3 [get_ports {hdmi_r_p}]
+set_property PACKAGE_PIN V3 [get_ports {hdmi_r_n}]
 set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}]
 set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}]
-set_property PACKAGE_PIN U3 [get_ports {hdmi_b_p}]
-set_property PACKAGE_PIN V3 [get_ports {hdmi_b_n}]
+set_property PACKAGE_PIN R3 [get_ports {hdmi_b_p}]
+set_property PACKAGE_PIN R2 [get_ports {hdmi_b_n}]
 set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}]
 set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}]
 
@@ -53,8 +53,8 @@ set_property PACKAGE_PIN N18 [get_ports {video[2]}]
 set_property PACKAGE_PIN K18 [get_ports {video[3]}]
 set_property PACKAGE_PIN M18 [get_ports {video[4]}]
 set_property PACKAGE_PIN M15 [get_ports {video[5]}]
-#set_property PACKAGE_PIN U20 [get_ports {video[6]}]
-#set_property PACKAGE_PIN T21 [get_ports {video[7]}]
+set_property PACKAGE_PIN U20 [get_ports {video[6]}]
+set_property PACKAGE_PIN T21 [get_ports {video[7]}]
 
 set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
@@ -62,8 +62,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
 
 set_property PACKAGE_PIN W19 [get_ports {pclk_in}]
 set_property PACKAGE_PIN R18 [get_ports {vsync_in}]
@@ -74,7 +74,6 @@ set_property PACKAGE_PIN P15 [get_ports {b_out}]
 set_property PACKAGE_PIN P14 [get_ports {i_clk_out}]
 set_property PACKAGE_PIN V17 [get_ports {hsync_out}]
 set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
-set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
 
 
 set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}]
@@ -103,11 +102,13 @@ create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m]
 set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
 
 # High-speed configuration so FPGA is up in time to negotiate with PCIe root complex
-set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design]
+#set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-set_property CONFIG_MODE SPIx4 [current_design]
-set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+#set_property CONFIG_MODE SPIx4 [current_design]
+#set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+#set_property BITSTREAM.GENERAL.COMPRESS FALSE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]
+
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
diff --git a/fpga/hp_lcd_driver/scripts/xilinx_bit_to_bin.pl b/fpga/hp_lcd_driver/scripts/xilinx_bit_to_bin.pl
new file mode 100755
index 0000000..317a09e
--- /dev/null
+++ b/fpga/hp_lcd_driver/scripts/xilinx_bit_to_bin.pl
@@ -0,0 +1,80 @@
+#!/usr/bin/env perl
+
+use strict;
+use warnings;
+
+use Data::Dumper;
+
+sub read_file($) {
+    my ($name) = @_;
+
+    my $fh = new IO::File "<" . $name;
+    binmode $fh;
+    local $/;
+    my $guts = $fh->getline;
+    $fh->close;
+    undef $fh;
+
+    return $guts;
+}
+
+sub dump_file($$) {
+    my ( $name, $guts ) = @_;
+
+    my $fh = new IO::File ">" . $name;
+    binmode $fh;
+    $fh->print($guts);
+    $fh->close;
+    undef $fh;
+}
+
+sub read_section($$$){
+	my ($in,$ll,$t)=@_;
+
+	die "file ends too soon"  if length($$in)<($ll+1);
+	die "section type mismatch" if substr($$in,0,1) ne $t;
+
+	my $ls= substr($$in,1,$ll);
+	$$in=substr($$in,1+$ll);
+
+	my $l=0;
+	for ( my $i = 0; $i < length($ls); $i++ ) {
+		$l<<=8;
+    		$l=$l+ord( substr( $ls, $i, 1));
+	}
+
+
+
+	die "file ends too soon" if length($$in)<$l;
+
+	my $v=substr($$in,0,$l);
+	$$in=substr($$in,$l);
+
+	return $v;
+}
+
+
+
+
+my $in=read_file($ARGV[0]);
+
+die "file ends too soon" if length($in)<13;
+
+$in=substr($in,13);
+
+
+my $file_name=read_section(\$in,2,'a');
+my $part_name=read_section(\$in,2,'b');
+my $date=read_section(\$in,2,'c');
+my $time=read_section(\$in,2,'d');
+my $data=read_section(\$in,4,'e');
+
+print "partname=$part_name\n";
+
+my $b=unpack('b*',$data);
+$data=pack('B*',$b);
+
+
+dump_file($ARGV[1],$data);
+
+
diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl
index 82186e1..6e4c171 100644
--- a/fpga/hp_lcd_driver/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver/vram_artix7.vhdl
@@ -19,8 +19,14 @@ end vram;
 
 architecture beh of vram is
     signal wr_en_v : std_logic_vector(0 downto 0);
+    signal wr_data_6 : std_logic_vector(5 downto 0);
+    signal rd_data_6 : std_logic_vector(5 downto 0);
 begin
 
+    wr_data_6 <= "00" & wr_data;
+    rd_data <= rd_data_6(3 downto 0);
+
+
     wr_en_v(0) <= wr_en;
 
     bmg0 : entity work.blk_mem_gen_0
@@ -30,9 +36,9 @@ begin
             clka  => wr_clk,
             wea   => wr_en_v,
             addra => wr_addr,
-            dina  => wr_data,
+            dina  => wr_data_6,
             clkb  => rd_clk,
-            doutb => rd_data,
+            doutb => rd_data_6,
             addrb => rd_addr
             );
 end beh;