Wednesday's progress - happy working a7, changes to bt475 hat

19 files changed, 3005 insertions, 911 deletions

diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index e9f1df7..458951d 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -1,7 +1,10 @@
 TARGETS= rando_a7 #smh-ac415b  #spartan6 #ep4ce6 smh-ac415
 #fish:smh-ac415
 
-default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
+better_default: build_rando_a7/hp_lcd_driver.svf
+	./prog_a7
+
+default: ${TARGETS:%=build_%/hp_lcd_driver.svf} 
 
 
 
@@ -9,8 +12,6 @@ smh-ac415: build_smh-ac415/hp_lcd_driver.svf
 spartan6: build_spartan6/hp_lcd_driver.svf
 rando_a7: build_rando_a7/out/hp_lcd_driver.bit
 
-
-
 build_%/hp_lcd_driver.svf: dummy
 	${MAKE} -f ${@:build_%/hp_lcd_driver.svf=%}.mk
 
diff --git a/fpga/hp_lcd_driver/artix7.mk b/fpga/hp_lcd_driver/artix7.mk
index 578468c..8c83e78 100644
--- a/fpga/hp_lcd_driver/artix7.mk
+++ b/fpga/hp_lcd_driver/artix7.mk
@@ -7,6 +7,7 @@ IP= \
 
 
 BIT=${BUILD}/out/hp_lcd_driver.bit
+BIN=${BUILD}/out/hp_lcd_driver.bin
 
 IP_STAMP=${IP:artix7_ip/%.tcl=${BUILD}/ip/%/stamp}
 SRCS= ${IP} \
@@ -35,11 +36,12 @@ SRCS= ${IP} \
 
 OPENOCD=openocd -f openocd/${BOARD}.cfg
 
-default:  ${BUILD}/build.stamp
+default:  ${BUILD}/build.stamp 
 
 ${BUILD}/build.stamp:${SRCS} ${IP_STAMP}
 	mkdir -p ${BUILD}
 	(cd ${BUILD} && BOARD=${BOARD} ../scripts/vivado -mode batch  -source ../artix7_hp_lcd_driver.tcl)
+	scripts/xilinx_bit_to_bin.pl ${BIT} ${BIN}
 	touch $@
 
 ${BUILD}/ip/%/stamp:artix7_ip/%.tcl
diff --git a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
index 684e493..3859382 100644
--- a/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
+++ b/fpga/hp_lcd_driver/artix7_hp_lcd_driver.tcl
@@ -24,6 +24,7 @@ read_vhdl -vhdl2008 -library work { ../clkgen_artix7.vhdl ../debounce.vhdl ../de
 
 set generics {}
 append generics { } "video_width=$video_width"
+append generics { } "input_video_width=$input_video_width"
 append generics { } "BOARD=\"$board\""
 append generics { } "use_pclk=$use_pclk"
 
diff --git a/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl b/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl
index a49c8f2..dda6633 100644
--- a/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl
+++ b/fpga/hp_lcd_driver/artix7_ip/mmcm_0.tcl
@@ -9,12 +9,12 @@ set_property -dict [list \
 	CONFIG.CLKOUT2_USED {true} \
 	CONFIG.CLKOUT3_USED {true} \
 	CONFIG.CLKOUT4_USED {true} \
-	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {240} \
-	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {80} \
-	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {48} \
-	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {24} \
+	CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {260} \
+	CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {86.667} \
+	CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {52} \
+	CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {26} \
 	CONFIG.CLKIN1_JITTER_PS {200.0} \
-	CONFIG.MMCM_CLKFBOUT_MULT_F {24.000} \
+	CONFIG.MMCM_CLKFBOUT_MULT_F {26.000} \
 	CONFIG.MMCM_CLKIN1_PERIOD {20.000} \
 	CONFIG.MMCM_CLKIN2_PERIOD {10.0} \
 	CONFIG.MMCM_CLKOUT0_DIVIDE_F {5.000} \
diff --git a/fpga/hp_lcd_driver/flash_a7 b/fpga/hp_lcd_driver/flash_a7
new file mode 100755
index 0000000..caf46ec
--- /dev/null
+++ b/fpga/hp_lcd_driver/flash_a7
@@ -0,0 +1,5 @@
+#!/bin/bash
+BIN=./build_rando_a7/out/hp_lcd_driver.bit
+SPIBIT=../../openocd/bscan_spi/bscan_spi_xc7a35t.bit
+../../openocd/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f cpld/xilinx-xc7.cfg -f cpld/jtagspi.cfg  -c init -c "jtagspi_init xc7.pld ${SPIBIT}; jtagspi_program $BIN 0" -c shutdown
+
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index 95a38a1..94199b9 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -11,7 +11,8 @@ use work.all;
 
 
 entity hp_lcd_driver is
-    generic (video_width    : natural := 2;
+    generic (input_video_width    : natural := 2;
+	     video_width : natural :=2;
              addr_width     : natural := 18;
              phase_slip     : natural := 320;
              i_clk_multiple : natural := 4;
@@ -19,7 +20,7 @@ entity hp_lcd_driver is
              target         : string  := "artix7");
     port (clk_50m   : in  std_logic;
           sys_rst_n : in  std_logic;
-          video     : in  std_logic_vector(video_width -1 downto 0);
+          video     : in  std_logic_vector(input_video_width -1 downto 0);
           hsync_in  : in  std_logic;
           vsync_in  : in  std_logic;
           pclk_in   : in  std_logic;
@@ -44,8 +45,10 @@ end hp_lcd_driver;
 
 architecture Behavioral of hp_lcd_driver is
 
+    signal video_lut : std_logic_vector (video_width-1 downto 0);
     signal wr_addr : std_logic_vector(addr_width-1 downto 0);
     signal wr_data : std_logic_vector(video_width-1 downto 0);
+    signal wr_data_b : std_logic_vector(video_width-1 downto 0);
     signal wr_en   : std_logic;
 
     signal rd_addr : std_logic_vector(addr_width-1 downto 0);
@@ -98,6 +101,16 @@ begin
             );
 
 
+video_lut <= "1111" when video(0)='1' else
+	     "1011" when video(1)='1' else
+	     "1100" when video(2)='1' else
+	     "1010" when video(3)='1' else
+	     "0011" when video(4)='1' else
+	     "1110" when video(5)='1' else
+	     "1001" when video(6)='1' else
+	     "1101" when video(7)='1' else
+	     "0000";
+
 
     process (i_clk, sys_rst_n)
     begin
@@ -136,7 +149,7 @@ begin
             clk_multiple  => i_clk_multiple,
 -- HP54502A
 --            phase         => 1,
---            h_front_porch => 210,
+--            h_front_porch => 200,
 --            h_active      => 592,
 --            v_front_porch => 1,
 --            v_active      => 384,
@@ -145,7 +158,7 @@ begin
 --            v_stride      => 262143,
 -- HP54522A
             phase         => 1,
-            h_front_porch => 213,
+            h_front_porch => 190,
             h_active      => 640,
             v_front_porch => 22,
             v_active      => 384,
@@ -158,7 +171,7 @@ begin
         port map (
             sys_rst_n => sys_rst_n,
             clk       => i_clk,
-            video_in  => video,
+            video_in  => video_lut,
             pclk_in   => pclk_in,
             hsync_in  => not hsync_in,
             vsync_in  => not vsync_in,
@@ -196,6 +209,7 @@ begin
 --    wr_data <="01" when (h=0) or (h=383) or (v=0) or (v=591)
 --              else "00";
 --
+
     vram0 : entity work.vram
         generic map (
             video_width => video_width,
@@ -216,9 +230,24 @@ begin
 --   r<=x"00";
 --   b<=x"00";
 
-    r <= rd_data(1 downto 0) & "000000";
-    g <= rd_data(3 downto 2) & "000000";
-    b <= rd_data(5 downto 4) & "000000";
+
+
+
+    r<=x"ff" when rd_data(0)='1' else
+	 x"00";
+
+--    r<=x"ff" when rd_data(0)='1' and rd_data(3)='1' else
+--	 x"80" when rd_data(0)='1' else
+--	 x"00";
+
+    g<=x"ff" when rd_data(1)='1' and rd_data(3)='1' else
+	 x"80" when rd_data(1)='1' else
+	 x"00";
+    b<=x"ff" when rd_data(2)='1' and rd_data(3)='1' else
+	 x"80" when rd_data(2)='1' else
+	 x"00";
+
+    
 
 --"ff" when rd_data(1) = '1' else
 --         x"80" when rd_data(0) = '1' else
@@ -261,7 +290,7 @@ begin
 -- HP54522A
             h_active     => 384,
             h_sync_start => 400,
-            h_sync_end   => 440,
+            h_sync_end   => 456,
             h_total      => 660,
 --            h_active     => 417,
 --            h_sync_start => 440,
@@ -294,7 +323,7 @@ begin
             clk_x2     => o_clk_x2,
             clk_phy    => o_clk_phy,
             sys_rst_n  => sys_rst_n,
-            vsync_in   => vsync_in,
+            vsync_in   => not vsync_in,
             r_in       => r,
             g_in       => g,
             b_in       => b,
diff --git a/fpga/hp_lcd_driver/input_formatter.vhdl b/fpga/hp_lcd_driver/input_formatter.vhdl
index 35916f5..f8b27c2 100644
--- a/fpga/hp_lcd_driver/input_formatter.vhdl
+++ b/fpga/hp_lcd_driver/input_formatter.vhdl
@@ -72,7 +72,7 @@ begin
         port map(
             clk => clk,
             sig => pclk,
-            e   => pclk_ne,
+            ne  => pclk_ne,
             pe  => pclk_pe);
 
 
@@ -131,7 +131,7 @@ begin
                         wren  <= '0';
                     end if;
                 else
-		    wren <= pclk_pe;
+		    wren <= pclk_ne;
                 end if;
 
                 if wren = '1' then
diff --git a/fpga/hp_lcd_driver/input_stage.vhdl b/fpga/hp_lcd_driver/input_stage.vhdl
index c124a59..1316b6e 100644
--- a/fpga/hp_lcd_driver/input_stage.vhdl
+++ b/fpga/hp_lcd_driver/input_stage.vhdl
@@ -71,7 +71,7 @@ begin
 
 
     pclk_sync : entity work.synchronizer
-        generic map(stages => sync_stages)
+        generic map(stages => sync_stages + debounce_stages+1)
         port map (
             clk => clk,
             i   => pclk_in,
@@ -95,13 +95,6 @@ begin
             );
 
 
-    pclk_debounce : entity work.debounce
-        generic map(stages => debounce_stages)
-        port map(
-            clk => clk,
-            i   => s_pclk,
-            o   => d_pclk);
-
     hsync_debounce : entity work.debounce
         generic map(stages => debounce_stages)
         port map(
@@ -135,7 +128,7 @@ begin
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
-            pclk      => d_pclk,
+            pclk      => s_pclk,
             hsync     => d_hsync,
             vsync     => d_vsync,
             addr_out  => addr,
diff --git a/fpga/hp_lcd_driver/output_formatter.vhdl b/fpga/hp_lcd_driver/output_formatter.vhdl
index 558c222..1f9e89f 100644
--- a/fpga/hp_lcd_driver/output_formatter.vhdl
+++ b/fpga/hp_lcd_driver/output_formatter.vhdl
@@ -26,8 +26,7 @@ entity output_formatter is
         blank_out : out std_logic;
         vsync_out : out std_logic;
         hsync_out : out std_logic;
-        h_grid    : out std_logic;
-        v_grid    : out std_logic
+        grid_out  : out std_logic
         );
 end output_formatter;
 
@@ -42,11 +41,11 @@ architecture beh of output_formatter is
     signal h : natural;
     signal v : natural;
 
-
     signal blank  : std_logic;
     signal vblank : std_logic;
     signal vsync  : std_logic;
     signal hsync  : std_logic;
+    signal grid  : std_logic;
 
 
 begin
@@ -71,7 +70,7 @@ begin
                 if v /= (v_total-1) then
                     v <= v+1;
                     h <= 0;
-                else                    --if vsync_in_ne = '1' then
+                else  --if vsync_in_ne = '1' then -- JMM if we synchronise the vsyncs then the display goes to sleep
                     h <= 0;
                     v <= 0;
                 end if;
@@ -89,17 +88,16 @@ begin
             vblank   <= '1';
             vsync    <= '0';
             hsync    <= '0';
+	    grid <='0';
         elsif rising_edge(clk) then
-
             if h = 0 then
                 if v = 0 then
-                    --row_addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
                     row_addr <= std_logic_vector(to_unsigned(v_stride, row_addr'length));
-                    --addr <= std_logic_vector(to_unsigned(-10*v_stride,row_addr'length));
                     addr     <= (others => '0');
+                    --addr     <= std_logic_vector(to_unsigned(h_stride, addr'length));
                     blank    <= '0';
                     vblank   <= '0';
-                elsif v = v_active then
+                elsif v = v_active  then
                     vblank <= '1';
                 elsif v = v_sync_start then
                     vsync <= '1';
@@ -108,7 +106,8 @@ begin
                 else
                     blank    <= vblank;
                     row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
-                    addr     <= row_addr;
+		    addr <= row_addr;
+                    --addr     <= std_logic_vector(unsigned(row_addr)+h_stride);
                 end if;
             elsif h = h_active then
                 blank <= '1';
@@ -119,22 +118,27 @@ begin
             else
                 addr <= std_logic_vector(unsigned(addr)+h_stride);
             end if;
+
+    grid <= '1' when h  = 0 else
+	'1' when h=10 else
+	'1' when h=h_active-11 else
+	'1' when h=h_active-1 else
+        '1' when v=0 else
+	'1' when v=10 else
+	'1' when v=v_active-11 else
+	'1' when v=v_active-1 else
+	'0';
+
         end if;
     end process;
 
-    h_grid <= '1' when (h mod 32) = 0
---    h_grid <= '1' when (h = 0) or (h = (h_active-1))
-else '0';
-
-    v_grid <= '1' when (v mod 32) = 0
---    v_grid <= '1' when (v = 0) or (v = (v_active-1))
-else '0';
 
 
     addr_out  <= addr;
     blank_out <= blank;
     hsync_out <= hsync;
     vsync_out <= vsync;
+    grid_out <= grid;
 
 end beh;
 
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index 56f4ae4..b43dc50 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -75,8 +75,7 @@ architecture beh of output_stage is
     signal g : std_logic_vector(7 downto 0);
     signal b : std_logic_vector(7 downto 0);
 
-    signal h_grid : std_logic;
-    signal v_grid : std_logic;
+    signal grid : std_logic;
 
     signal r_p10 : std_logic_vector(9 downto 0);
     signal g_p10 : std_logic_vector(9 downto 0);
@@ -125,59 +124,49 @@ begin
             blank_out => blank,
             vsync_out => vsync,
             hsync_out => hsync,
-            h_grid    => h_grid,
-            v_grid    => v_grid
+            grid_out    => grid
             );
 
 
     addr_out <= addr;
 
---    dg : entity work.delay
---        generic map(stages => 1)
---        port map (
---            clk => clk,
---            i   => h_grid or v_grid,
---            o   => grid_d
---            );
+    dg : entity work.delay
+        generic map(stages => 2)
+        port map (
+            clk => clk,
+            i   => grid, 
+            o   => grid_d
+            );
 
-    r <= r_in;
+    r <=  r_in;
     g <= g_in;
     b <= b_in;
 
 
 
---    b<=x"00" when v_grid='0'
---          else x"ff";
-
---    r<=x"00" when h_grid='0'
---          else x"ff";
-
---    b<=x"00" when v_grid='0' and h_grid='0'
---          else x"ff";
-
---
---    dh : entity work.delay
---        generic map(stages => 10)
---        port map (
---            clk => clk,
---            i   => hsync,
---            o   => hsync_d
---            );
---
---
---
---    dv : entity work.delay
---        generic map(stages => 10)
---        port map (
---            clk => clk,
---            i   => vsync,
---            o   => vsync_d
---            );
---
---
---
-    dn : entity work.delay
-        generic map(stages => 1)
+
+    dh : entity work.delay
+        generic map(stages => 2)
+        port map (
+            clk => clk,
+            i   => hsync,
+            o   => hsync_d
+            );
+
+
+
+    dv : entity work.delay
+        generic map(stages => 2)
+        port map (
+            clk => clk,
+            i   => vsync,
+            o   => vsync_d
+            );
+
+
+
+    db : entity work.delay
+        generic map(stages => 2)
         port map (
             clk => clk,
             i   => blank,
@@ -185,9 +174,6 @@ begin
             );
 
 
-    hsync_d <= hsync;
-    vsync_d <= vsync;
-
 
     analog : entity work.output_analog
         port map(
diff --git a/fpga/hp_lcd_driver/prog_a7 b/fpga/hp_lcd_driver/prog_a7
index c10ee8f..6421562 100755
--- a/fpga/hp_lcd_driver/prog_a7
+++ b/fpga/hp_lcd_driver/prog_a7
@@ -1,4 +1,4 @@
 #!/bin/bash
-BIT=./build-rando_a7/out/hp_lcd_driver.bit
+BIT=./build_rando_a7/out/hp_lcd_driver.bit
 ../../openocd/prefix/bin/openocd -f interface/altera-usb-blaster.cfg -f cpld/xilinx-xc7.cfg -c init -c "pld load xc7.pld $BIT" -c shutdown
 
diff --git a/fpga/hp_lcd_driver/rando_a7.tcl b/fpga/hp_lcd_driver/rando_a7.tcl
index cfaa74d..cb14260 100644
--- a/fpga/hp_lcd_driver/rando_a7.tcl
+++ b/fpga/hp_lcd_driver/rando_a7.tcl
@@ -2,4 +2,5 @@
 set part_num "xc7a35tfgg484-2"
 set normal_xdc "../rando_a7.xdc"
 set use_pclk 1
-set video_width 6
+set input_video_width 8
+set video_width 4
diff --git a/fpga/hp_lcd_driver/rando_a7.xdc b/fpga/hp_lcd_driver/rando_a7.xdc
index 04b2cac..3f3c24d 100644
--- a/fpga/hp_lcd_driver/rando_a7.xdc
+++ b/fpga/hp_lcd_driver/rando_a7.xdc
@@ -9,12 +9,12 @@ set_property IOSTANDARD LVCMOS33 [get_ports {led}]
 #set_property PACKAGE_PIN T1 [get_ports {led_1}]
 #set_property IOSTANDARD LVCMOS33 [get_ports {led_1}]
 
-set_property PACKAGE_PIN R3 [get_ports {hdmi_r_p}]
-set_property PACKAGE_PIN R2 [get_ports {hdmi_r_n}]
+set_property PACKAGE_PIN U3 [get_ports {hdmi_r_p}]
+set_property PACKAGE_PIN V3 [get_ports {hdmi_r_n}]
 set_property PACKAGE_PIN R6 [get_ports {hdmi_g_p}]
 set_property PACKAGE_PIN T6 [get_ports {hdmi_g_n}]
-set_property PACKAGE_PIN U3 [get_ports {hdmi_b_p}]
-set_property PACKAGE_PIN V3 [get_ports {hdmi_b_n}]
+set_property PACKAGE_PIN R3 [get_ports {hdmi_b_p}]
+set_property PACKAGE_PIN R2 [get_ports {hdmi_b_n}]
 set_property PACKAGE_PIN Y3 [get_ports {hdmi_c_p}]
 set_property PACKAGE_PIN AA3 [get_ports {hdmi_c_n}]
 
@@ -53,8 +53,8 @@ set_property PACKAGE_PIN N18 [get_ports {video[2]}]
 set_property PACKAGE_PIN K18 [get_ports {video[3]}]
 set_property PACKAGE_PIN M18 [get_ports {video[4]}]
 set_property PACKAGE_PIN M15 [get_ports {video[5]}]
-#set_property PACKAGE_PIN U20 [get_ports {video[6]}]
-#set_property PACKAGE_PIN T21 [get_ports {video[7]}]
+set_property PACKAGE_PIN U20 [get_ports {video[6]}]
+set_property PACKAGE_PIN T21 [get_ports {video[7]}]
 
 set_property IOSTANDARD LVCMOS33 [get_ports {video[0]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[1]}]
@@ -62,8 +62,8 @@ set_property IOSTANDARD LVCMOS33 [get_ports {video[2]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[3]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[4]}]
 set_property IOSTANDARD LVCMOS33 [get_ports {video[5]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
-#set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {video[7]}]
 
 set_property PACKAGE_PIN W19 [get_ports {pclk_in}]
 set_property PACKAGE_PIN R18 [get_ports {vsync_in}]
@@ -74,7 +74,6 @@ set_property PACKAGE_PIN P15 [get_ports {b_out}]
 set_property PACKAGE_PIN P14 [get_ports {i_clk_out}]
 set_property PACKAGE_PIN V17 [get_ports {hsync_out}]
 set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
-set_property PACKAGE_PIN N13 [get_ports {vsync_out}]
 
 
 set_property IOSTANDARD LVCMOS33 [get_ports {pclk_in}]
@@ -103,11 +102,13 @@ create_clock -period 20.000 -name pcie_clkin [get_ports clk_50m]
 set_property BITSTREAM.CONFIG.OVERTEMPPOWERDOWN ENABLE [current_design]
 
 # High-speed configuration so FPGA is up in time to negotiate with PCIe root complex
-set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design]
+#set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN Div-1 [current_design]
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-set_property CONFIG_MODE SPIx4 [current_design]
-set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
-set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+#set_property CONFIG_MODE SPIx4 [current_design]
+#set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
+#set_property BITSTREAM.GENERAL.COMPRESS FALSE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 22 [current_design]
+
 
 set_property CONFIG_VOLTAGE 3.3 [current_design]
 set_property CFGBVS VCCO [current_design]
diff --git a/fpga/hp_lcd_driver/scripts/xilinx_bit_to_bin.pl b/fpga/hp_lcd_driver/scripts/xilinx_bit_to_bin.pl
new file mode 100755
index 0000000..317a09e
--- /dev/null
+++ b/fpga/hp_lcd_driver/scripts/xilinx_bit_to_bin.pl
@@ -0,0 +1,80 @@
+#!/usr/bin/env perl
+
+use strict;
+use warnings;
+
+use Data::Dumper;
+
+sub read_file($) {
+    my ($name) = @_;
+
+    my $fh = new IO::File "<" . $name;
+    binmode $fh;
+    local $/;
+    my $guts = $fh->getline;
+    $fh->close;
+    undef $fh;
+
+    return $guts;
+}
+
+sub dump_file($$) {
+    my ( $name, $guts ) = @_;
+
+    my $fh = new IO::File ">" . $name;
+    binmode $fh;
+    $fh->print($guts);
+    $fh->close;
+    undef $fh;
+}
+
+sub read_section($$$){
+	my ($in,$ll,$t)=@_;
+
+	die "file ends too soon"  if length($$in)<($ll+1);
+	die "section type mismatch" if substr($$in,0,1) ne $t;
+
+	my $ls= substr($$in,1,$ll);
+	$$in=substr($$in,1+$ll);
+
+	my $l=0;
+	for ( my $i = 0; $i < length($ls); $i++ ) {
+		$l<<=8;
+    		$l=$l+ord( substr( $ls, $i, 1));
+	}
+
+
+
+	die "file ends too soon" if length($$in)<$l;
+
+	my $v=substr($$in,0,$l);
+	$$in=substr($$in,$l);
+
+	return $v;
+}
+
+
+
+
+my $in=read_file($ARGV[0]);
+
+die "file ends too soon" if length($in)<13;
+
+$in=substr($in,13);
+
+
+my $file_name=read_section(\$in,2,'a');
+my $part_name=read_section(\$in,2,'b');
+my $date=read_section(\$in,2,'c');
+my $time=read_section(\$in,2,'d');
+my $data=read_section(\$in,4,'e');
+
+print "partname=$part_name\n";
+
+my $b=unpack('b*',$data);
+$data=pack('B*',$b);
+
+
+dump_file($ARGV[1],$data);
+
+
diff --git a/fpga/hp_lcd_driver/vram_artix7.vhdl b/fpga/hp_lcd_driver/vram_artix7.vhdl
index 82186e1..6e4c171 100644
--- a/fpga/hp_lcd_driver/vram_artix7.vhdl
+++ b/fpga/hp_lcd_driver/vram_artix7.vhdl
@@ -19,8 +19,14 @@ end vram;
 
 architecture beh of vram is
     signal wr_en_v : std_logic_vector(0 downto 0);
+    signal wr_data_6 : std_logic_vector(5 downto 0);
+    signal rd_data_6 : std_logic_vector(5 downto 0);
 begin
 
+    wr_data_6 <= "00" & wr_data;
+    rd_data <= rd_data_6(3 downto 0);
+
+
     wr_en_v(0) <= wr_en;
 
     bmg0 : entity work.blk_mem_gen_0
@@ -30,9 +36,9 @@ begin
             clka  => wr_clk,
             wea   => wr_en_v,
             addra => wr_addr,
-            dina  => wr_data,
+            dina  => wr_data_6,
             clkb  => rd_clk,
-            doutb => rd_data,
+            doutb => rd_data_6,
             addrb => rd_addr
             );
 end beh;
diff --git a/openocd/bscan_spi/bscan_spi_xc7a35t.bit b/openocd/bscan_spi/bscan_spi_xc7a35t.bit
new file mode 100644
index 0000000..be649f0
--- /dev/null
+++ b/openocd/bscan_spi/bscan_spi_xc7a35t.bit
diff --git a/pcbs/bt475-interface/bt475-interface.kicad_pcb b/pcbs/bt475-interface/bt475-interface.kicad_pcb
index 5a34d02..87b56c1 100644
--- a/pcbs/bt475-interface/bt475-interface.kicad_pcb
+++ b/pcbs/bt475-interface/bt475-interface.kicad_pcb
@@ -105,40 +105,40 @@
 	(net 23 "Net-(U1-P7)")
 	(net 24 "Net-(U1-P2)")
 	(net 25 "Net-(U1-CLOCK)")
-	(net 26 "Net-(J2-Pin_14)")
-	(net 27 "Net-(J2-Pin_13)")
-	(net 28 "Net-(J2-Pin_16)")
-	(net 29 "Net-(J2-Pin_15)")
-	(net 30 "Net-(J2-Pin_6)")
-	(net 31 "Net-(J2-Pin_8)")
-	(net 32 "Net-(J2-Pin_5)")
+	(net 26 "/P5")
+	(net 27 "/HSYNC")
+	(net 28 "/P7")
+	(net 29 "/PCLK")
+	(net 30 "/P3")
+	(net 31 "/~{BLANK}")
+	(net 32 "/P1")
 	(net 33 "Net-(J2-Pin_12)")
-	(net 34 "Net-(J2-Pin_7)")
-	(net 35 "Net-(J2-Pin_10)")
+	(net 34 "/P2")
+	(net 35 "/P4")
 	(net 36 "Net-(J2-Pin_11)")
 	(net 37 "Net-(J2-Pin_9)")
 	(net 38 "Net-(J1-Pin_1)")
 	(net 39 "Net-(J1-Pin_2)")
 	(net 40 "Net-(U1-~{BLANK})")
 	(net 41 "Net-(U1-~{SYNC})")
-	(net 42 "Net-(J3-Pin_16)")
-	(net 43 "Net-(J3-Pin_2)")
-	(net 44 "Net-(J3-Pin_14)")
-	(net 45 "Net-(J3-Pin_18)")
-	(net 46 "Net-(J3-Pin_10)")
-	(net 47 "Net-(J3-Pin_6)")
-	(net 48 "Net-(J3-Pin_8)")
-	(net 49 "Net-(J3-Pin_12)")
-	(net 50 "Net-(J3-Pin_20)")
-	(net 51 "Net-(J3-Pin_22)")
-	(net 52 "Net-(J3-Pin_24)")
-	(net 53 "Net-(J3-Pin_26)")
-	(net 54 "Net-(J3-Pin_4)")
+	(net 42 "/P0")
+	(net 43 "/VSYNC")
+	(net 44 "/P6")
+	(net 45 "/~{SYNC}")
+	(net 46 "/D5")
+	(net 47 "/~{RD}")
+	(net 48 "/D4")
+	(net 49 "/D6")
+	(net 50 "/D7")
+	(net 51 "/RS0")
+	(net 52 "/~{WR}")
+	(net 53 "/D2")
+	(net 54 "/RS2")
 	(net 55 "+3.3V")
-	(net 56 "Net-(J2-Pin_3)")
-	(net 57 "Net-(J2-Pin_1)")
-	(net 58 "Net-(J2-Pin_4)")
-	(net 59 "Net-(J2-Pin_2)")
+	(net 56 "/D0")
+	(net 57 "/D1")
+	(net 58 "/D3")
+	(net 59 "/RS1")
 	(footprint "Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder"
 		(layer "F.Cu")
 		(uuid "00811913-29a1-4a81-9c76-802f919b5f49")
@@ -578,7 +578,7 @@
 			(roundrect_rratio 0.25)
 			(net 5 "+5V")
 			(pinfunction "VCCA")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "e26da042-f646-4315-8298-672d2e3142b1")
 		)
 		(pad "2" smd roundrect
@@ -688,7 +688,7 @@
 			(roundrect_rratio 0.25)
 			(net 2 "GND")
 			(pinfunction "GND")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "b7b8f6bd-f852-4b44-b199-06df76e43e9f")
 		)
 		(pad "13" smd roundrect
@@ -698,7 +698,7 @@
 			(roundrect_rratio 0.25)
 			(net 2 "GND")
 			(pinfunction "GND")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "b5c73bb8-ee5c-474d-8089-2df9a4035655")
 		)
 		(pad "14" smd roundrect
@@ -706,7 +706,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 28 "Net-(J2-Pin_16)")
+			(net 43 "/VSYNC")
 			(pinfunction "B8")
 			(pintype "bidirectional")
 			(uuid "42264737-1f57-404b-aefc-12ebf06c6060")
@@ -716,7 +716,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 29 "Net-(J2-Pin_15)")
+			(net 27 "/HSYNC")
 			(pinfunction "B7")
 			(pintype "bidirectional")
 			(uuid "7b2adc48-2733-40f8-86e2-ea5fe01d3e21")
@@ -726,7 +726,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 26 "Net-(J2-Pin_14)")
+			(net 31 "/~{BLANK}")
 			(pinfunction "B6")
 			(pintype "bidirectional")
 			(uuid "41ff0306-cb7d-45f5-a3b4-3f8fceaf2794")
@@ -736,7 +736,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 27 "Net-(J2-Pin_13)")
+			(net 45 "/~{SYNC}")
 			(pinfunction "B5")
 			(pintype "bidirectional")
 			(uuid "96bb8b22-5a01-4136-90ce-6087733c2f2c")
@@ -766,7 +766,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 35 "Net-(J2-Pin_10)")
+			(net 29 "/PCLK")
 			(pinfunction "B2")
 			(pintype "bidirectional")
 			(uuid "d6b2c000-a860-481e-a514-6256c6c9c3a4")
@@ -808,7 +808,7 @@
 			(roundrect_rratio 0.25)
 			(net 55 "+3.3V")
 			(pinfunction "VCCB")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "344ac7de-3165-48db-a7d9-2956cab5c49a")
 		)
 		(model "${KICAD8_3DMODEL_DIR}/Package_SO.3dshapes/TSSOP-24_4.4x7.8mm_P0.65mm.wrl"
@@ -1147,7 +1147,7 @@
 			(remove_unused_layers no)
 			(net 2 "GND")
 			(pinfunction "GND")
-			(pintype "power_out")
+			(pintype "power_in")
 			(uuid "93809a61-4394-4796-91d9-fc61a9a80981")
 		)
 		(pad "4" thru_hole circle
@@ -1158,7 +1158,7 @@
 			(remove_unused_layers no)
 			(net 5 "+5V")
 			(pinfunction "VAA")
-			(pintype "power_out")
+			(pintype "power_in")
 			(uuid "2d7401db-7d78-469e-ad97-20610b49f974")
 		)
 		(pad "5" thru_hole circle
@@ -1178,7 +1178,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 43 "Net-(J3-Pin_2)")
+			(net 47 "/~{RD}")
 			(pinfunction "~{RD}")
 			(pintype "output")
 			(uuid "de6e822c-6fc0-4a73-a9e1-c56f4bafca6c")
@@ -1200,7 +1200,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 47 "Net-(J3-Pin_6)")
+			(net 56 "/D0")
 			(pinfunction "D0")
 			(pintype "output")
 			(uuid "bfd7a9c8-d242-49ac-b264-1cd45298a015")
@@ -1211,7 +1211,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 48 "Net-(J3-Pin_8)")
+			(net 57 "/D1")
 			(pinfunction "D1")
 			(pintype "output")
 			(uuid "38c47451-e554-442b-b261-7e1d6f9392d8")
@@ -1222,7 +1222,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 46 "Net-(J3-Pin_10)")
+			(net 53 "/D2")
 			(pinfunction "D2")
 			(pintype "output")
 			(uuid "9af81706-b988-47f6-8ee9-9d3a0e724d14")
@@ -1233,7 +1233,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 49 "Net-(J3-Pin_12)")
+			(net 58 "/D3")
 			(pinfunction "D3")
 			(pintype "output")
 			(uuid "430cceaf-ca87-473f-a9dd-514cbb9cf037")
@@ -1244,7 +1244,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 44 "Net-(J3-Pin_14)")
+			(net 48 "/D4")
 			(pinfunction "D4")
 			(pintype "output")
 			(uuid "bdca3c82-020f-446c-9ebf-66585a5051d5")
@@ -1255,7 +1255,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 42 "Net-(J3-Pin_16)")
+			(net 46 "/D5")
 			(pinfunction "D5")
 			(pintype "output")
 			(uuid "05c9bb58-39c7-4e5b-8705-746d281c2a59")
@@ -1266,7 +1266,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 45 "Net-(J3-Pin_18)")
+			(net 49 "/D6")
 			(pinfunction "D6")
 			(pintype "output")
 			(uuid "70ce0124-774e-4e43-8b1f-331c0d1d99be")
@@ -1277,7 +1277,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 50 "Net-(J3-Pin_20)")
+			(net 50 "/D7")
 			(pinfunction "D7")
 			(pintype "output")
 			(uuid "da945f6e-74b3-4af2-8761-e68c3ea31337")
@@ -1288,7 +1288,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 54 "Net-(J3-Pin_4)")
+			(net 52 "/~{WR}")
 			(pinfunction "~{WR}")
 			(pintype "output")
 			(uuid "7ca03e02-1a3f-4f93-8b73-38f08b0c4947")
@@ -1299,7 +1299,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 51 "Net-(J3-Pin_22)")
+			(net 51 "/RS0")
 			(pinfunction "RS0")
 			(pintype "output")
 			(uuid "328cc873-c8b3-423f-96c5-40a953b87957")
@@ -1310,7 +1310,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 52 "Net-(J3-Pin_24)")
+			(net 59 "/RS1")
 			(pinfunction "RS1")
 			(pintype "output")
 			(uuid "8160f43d-b2a7-4e87-8faf-bd979efca897")
@@ -1321,7 +1321,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 53 "Net-(J3-Pin_26)")
+			(net 54 "/RS2")
 			(pinfunction "RS2")
 			(pintype "output")
 			(uuid "d3012d20-ce26-44f2-8233-d20f18e446f6")
@@ -1378,7 +1378,7 @@
 			(remove_unused_layers no)
 			(net 2 "GND")
 			(pinfunction "GND")
-			(pintype "power_out")
+			(pintype "power_in")
 			(uuid "570b709b-0f2f-437c-bfca-4adf7d4e979a")
 		)
 		(pad "25" thru_hole circle
@@ -1615,6 +1615,216 @@
 	)
 	(footprint "Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder"
 		(layer "F.Cu")
+		(uuid "499a8117-ae8a-4626-8055-9b98091e4d53")
+		(at 179.0375 65.4)
+		(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "capacitor handsolder")
+		(property "Reference" "C6"
+			(at 0 -1.43 360)
+			(layer "F.SilkS")
+			(uuid "54841a90-1fdd-49ea-91d7-25852e15f030")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "C"
+			(at 0 1.43 360)
+			(layer "F.Fab")
+			(uuid "ccfdcfb2-ff7d-4225-ba68-4a34421ce6f1")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Footprint" "Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "68397c32-fa89-4f7a-8e41-5d54dba9bebe")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "7eca059b-4f9e-4bc1-ad47-5b7763702726")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" "Unpolarized capacitor"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "5a9513d9-f637-432b-bc37-cf506118aa9c")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property ki_fp_filters "C_*")
+		(path "/6830cf4e-b6bc-4819-bb1d-73d5ea5f02a5")
+		(sheetname "Root")
+		(sheetfile "bt475-interface.kicad_sch")
+		(attr smd)
+		(fp_line
+			(start -0.146267 -0.51)
+			(end 0.146267 -0.51)
+			(stroke
+				(width 0.12)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "4b6e53ed-6557-4a2c-9fda-d9f628f243de")
+		)
+		(fp_line
+			(start -0.146267 0.51)
+			(end 0.146267 0.51)
+			(stroke
+				(width 0.12)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "2bdf0890-64b5-4843-a6ea-6c428e5b9c79")
+		)
+		(fp_line
+			(start -1.65 -0.73)
+			(end 1.65 -0.73)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "F.CrtYd")
+			(uuid "d19694bb-9709-4a8a-b7bf-98d328bd3eeb")
+		)
+		(fp_line
+			(start -1.65 0.73)
+			(end -1.65 -0.73)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "F.CrtYd")
+			(uuid "4ac7b987-4b7b-441e-9577-d428861d6a49")
+		)
+		(fp_line
+			(start 1.65 -0.73)
+			(end 1.65 0.73)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "F.CrtYd")
+			(uuid "72011e2a-cd89-4727-aced-154b0074ab8c")
+		)
+		(fp_line
+			(start 1.65 0.73)
+			(end -1.65 0.73)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "F.CrtYd")
+			(uuid "ee64d303-f13f-4a3e-85ee-1cd4a2f67c6a")
+		)
+		(fp_line
+			(start -0.8 -0.4)
+			(end 0.8 -0.4)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "F.Fab")
+			(uuid "c7c3e589-0078-45d8-9b49-bf6d30e8e822")
+		)
+		(fp_line
+			(start -0.8 0.4)
+			(end -0.8 -0.4)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "F.Fab")
+			(uuid "fea67283-a008-48f0-b335-8a05de1fb644")
+		)
+		(fp_line
+			(start 0.8 -0.4)
+			(end 0.8 0.4)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "F.Fab")
+			(uuid "6caa81c1-3ca3-49c0-b445-8094c69255a1")
+		)
+		(fp_line
+			(start 0.8 0.4)
+			(end -0.8 0.4)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "F.Fab")
+			(uuid "84c1e6da-7520-496c-8e3c-f9c917b3527e")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 0 360)
+			(layer "F.Fab")
+			(uuid "c61548c3-0b0f-41da-aa84-03c7989a41e2")
+			(effects
+				(font
+					(size 0.4 0.4)
+					(thickness 0.06)
+				)
+			)
+		)
+		(pad "1" smd roundrect
+			(at -0.8625 0)
+			(size 1.075 0.95)
+			(layers "F.Cu" "F.Paste" "F.Mask")
+			(roundrect_rratio 0.25)
+			(net 5 "+5V")
+			(pintype "passive")
+			(uuid "1408fd47-cd11-4483-839c-996eb1bcab62")
+		)
+		(pad "2" smd roundrect
+			(at 0.8625 0)
+			(size 1.075 0.95)
+			(layers "F.Cu" "F.Paste" "F.Mask")
+			(roundrect_rratio 0.25)
+			(net 2 "GND")
+			(pintype "passive")
+			(uuid "8407544a-8491-4fcc-8d4d-6476e1cfbf91")
+		)
+		(model "${KICAD8_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
+	(footprint "Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder"
+		(layer "F.Cu")
 		(uuid "4f87e84e-8e44-4b98-a04f-0316e0c4dde4")
 		(at 182.7 75.438)
 		(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
@@ -2052,7 +2262,7 @@
 			(roundrect_rratio 0.25)
 			(net 5 "+5V")
 			(pinfunction "VCCA")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "2b1efe14-65c2-4eaf-83cf-c8ed10757f31")
 		)
 		(pad "2" smd roundrect
@@ -2162,7 +2372,7 @@
 			(roundrect_rratio 0.25)
 			(net 2 "GND")
 			(pinfunction "GND")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "8110f8cc-d57a-440b-b102-f2a9761af8b4")
 		)
 		(pad "13" smd roundrect
@@ -2172,7 +2382,7 @@
 			(roundrect_rratio 0.25)
 			(net 2 "GND")
 			(pinfunction "GND")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "2d6774a4-bbb5-43df-90b9-6ef1713ca1e8")
 		)
 		(pad "14" smd roundrect
@@ -2180,7 +2390,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 31 "Net-(J2-Pin_8)")
+			(net 42 "/P0")
 			(pinfunction "B8")
 			(pintype "bidirectional")
 			(uuid "dc43bb75-d9a0-448c-8943-435595910190")
@@ -2190,7 +2400,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 34 "Net-(J2-Pin_7)")
+			(net 32 "/P1")
 			(pinfunction "B7")
 			(pintype "bidirectional")
 			(uuid "d6a1f5ef-19c1-46e2-bca8-20dce932e53f")
@@ -2200,7 +2410,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 30 "Net-(J2-Pin_6)")
+			(net 34 "/P2")
 			(pinfunction "B6")
 			(pintype "bidirectional")
 			(uuid "77408430-b399-4e8f-9c51-97670cdd8473")
@@ -2210,7 +2420,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 32 "Net-(J2-Pin_5)")
+			(net 30 "/P3")
 			(pinfunction "B5")
 			(pintype "bidirectional")
 			(uuid "7f04d8b7-e34b-45a9-a810-e41b5bc2a740")
@@ -2220,7 +2430,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 58 "Net-(J2-Pin_4)")
+			(net 35 "/P4")
 			(pinfunction "B4")
 			(pintype "bidirectional")
 			(uuid "cabfd779-d0cb-4027-a766-a384a1fcc34c")
@@ -2230,7 +2440,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 56 "Net-(J2-Pin_3)")
+			(net 26 "/P5")
 			(pinfunction "B3")
 			(pintype "bidirectional")
 			(uuid "c0a7c5bc-8ea1-49bc-9232-0f047d778964")
@@ -2240,7 +2450,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 59 "Net-(J2-Pin_2)")
+			(net 44 "/P6")
 			(pinfunction "B2")
 			(pintype "bidirectional")
 			(uuid "877ae5f3-8e57-48e9-87df-7ae4db281efb")
@@ -2250,7 +2460,7 @@
 			(size 1.475 0.4)
 			(layers "F.Cu" "F.Paste" "F.Mask")
 			(roundrect_rratio 0.25)
-			(net 57 "Net-(J2-Pin_1)")
+			(net 28 "/P7")
 			(pinfunction "B1")
 			(pintype "bidirectional")
 			(uuid "b9b54a5f-2d41-437f-baed-c0d48b20319b")
@@ -2282,7 +2492,7 @@
 			(roundrect_rratio 0.25)
 			(net 55 "+3.3V")
 			(pinfunction "VCCB")
-			(pintype "bidirectional")
+			(pintype "power_in")
 			(uuid "29cacbbd-8645-4c73-b7e0-38da8f04bcf7")
 		)
 		(model "${KICAD8_3DMODEL_DIR}/Package_SO.3dshapes/TSSOP-24_4.4x7.8mm_P0.65mm.wrl"
@@ -2553,7 +2763,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 57 "Net-(J2-Pin_1)")
+			(net 28 "/P7")
 			(pinfunction "Pin_1")
 			(pintype "passive")
 			(uuid "5a63220d-ec9a-46ad-b047-11b060e522ff")
@@ -2564,7 +2774,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 59 "Net-(J2-Pin_2)")
+			(net 44 "/P6")
 			(pinfunction "Pin_2")
 			(pintype "passive")
 			(uuid "e23d35df-e6a4-44fe-8671-aa9fe3870ad2")
@@ -2575,7 +2785,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 56 "Net-(J2-Pin_3)")
+			(net 26 "/P5")
 			(pinfunction "Pin_3")
 			(pintype "passive")
 			(uuid "394a09ca-e8f0-4216-bafa-130e8cfbc9c8")
@@ -2586,7 +2796,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 58 "Net-(J2-Pin_4)")
+			(net 35 "/P4")
 			(pinfunction "Pin_4")
 			(pintype "passive")
 			(uuid "81ac9d23-9a80-48ac-ada7-cd1733e5244d")
@@ -2597,7 +2807,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 32 "Net-(J2-Pin_5)")
+			(net 30 "/P3")
 			(pinfunction "Pin_5")
 			(pintype "passive")
 			(uuid "74889d01-0e98-4a9f-8f60-e2029b6a4079")
@@ -2608,7 +2818,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 30 "Net-(J2-Pin_6)")
+			(net 34 "/P2")
 			(pinfunction "Pin_6")
 			(pintype "passive")
 			(uuid "80b6c963-5f56-4825-9052-3ca5954ae4c8")
@@ -2619,7 +2829,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 34 "Net-(J2-Pin_7)")
+			(net 32 "/P1")
 			(pinfunction "Pin_7")
 			(pintype "passive")
 			(uuid "7cd6ed93-cac2-4882-8558-dbf6134e2234")
@@ -2630,7 +2840,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 31 "Net-(J2-Pin_8)")
+			(net 42 "/P0")
 			(pinfunction "Pin_8")
 			(pintype "passive")
 			(uuid "8e8afacb-629b-47cc-bf69-283bda3ae472")
@@ -2652,7 +2862,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 35 "Net-(J2-Pin_10)")
+			(net 29 "/PCLK")
 			(pinfunction "Pin_10")
 			(pintype "passive")
 			(uuid "6afd9b52-5cee-477b-92fe-7c506fed19f0")
@@ -2685,7 +2895,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 27 "Net-(J2-Pin_13)")
+			(net 45 "/~{SYNC}")
 			(pinfunction "Pin_13")
 			(pintype "passive")
 			(uuid "f43cd4a0-ace7-439b-ad63-1a85b72cbba3")
@@ -2696,7 +2906,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 26 "Net-(J2-Pin_14)")
+			(net 31 "/~{BLANK}")
 			(pinfunction "Pin_14")
 			(pintype "passive")
 			(uuid "7bfd0ec5-101f-40a3-a6ae-b2bf694539e7")
@@ -2707,7 +2917,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 29 "Net-(J2-Pin_15)")
+			(net 27 "/HSYNC")
 			(pinfunction "Pin_15")
 			(pintype "passive")
 			(uuid "56c6c1cf-24f0-4f96-9375-ccc48f37350b")
@@ -2718,7 +2928,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 28 "Net-(J2-Pin_16)")
+			(net 43 "/VSYNC")
 			(pinfunction "Pin_16")
 			(pintype "passive")
 			(uuid "c5ddc00b-9bdf-47d2-818e-db4272920569")
@@ -3299,7 +3509,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 43 "Net-(J3-Pin_2)")
+			(net 47 "/~{RD}")
 			(pinfunction "Pin_2")
 			(pintype "passive")
 			(uuid "00e57c4f-b7c7-4ccc-9261-a63aa9a543e9")
@@ -3321,7 +3531,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 54 "Net-(J3-Pin_4)")
+			(net 52 "/~{WR}")
 			(pinfunction "Pin_4")
 			(pintype "passive")
 			(uuid "3e08fd1d-1f4d-4530-a3b3-6584fbe571bf")
@@ -3343,7 +3553,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 47 "Net-(J3-Pin_6)")
+			(net 56 "/D0")
 			(pinfunction "Pin_6")
 			(pintype "passive")
 			(uuid "b5a6d86d-a7c9-4058-9357-f1e1bc42a6e5")
@@ -3365,7 +3575,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 48 "Net-(J3-Pin_8)")
+			(net 57 "/D1")
 			(pinfunction "Pin_8")
 			(pintype "passive")
 			(uuid "c8302d12-2080-463b-8d62-abd8cc91fff1")
@@ -3387,7 +3597,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 46 "Net-(J3-Pin_10)")
+			(net 53 "/D2")
 			(pinfunction "Pin_10")
 			(pintype "passive")
 			(uuid "41135ee8-3ca5-4a3a-b0b9-110943a1144f")
@@ -3409,7 +3619,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 49 "Net-(J3-Pin_12)")
+			(net 58 "/D3")
 			(pinfunction "Pin_12")
 			(pintype "passive")
 			(uuid "ccda0d6e-e3f7-4279-bc65-4052708714ba")
@@ -3431,7 +3641,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 44 "Net-(J3-Pin_14)")
+			(net 48 "/D4")
 			(pinfunction "Pin_14")
 			(pintype "passive")
 			(uuid "058f81c1-c8fe-47c1-9f3d-afb83c5d7d86")
@@ -3453,7 +3663,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 42 "Net-(J3-Pin_16)")
+			(net 46 "/D5")
 			(pinfunction "Pin_16")
 			(pintype "passive")
 			(uuid "00c07714-3d14-4a71-a89d-1626853fce15")
@@ -3475,7 +3685,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 45 "Net-(J3-Pin_18)")
+			(net 49 "/D6")
 			(pinfunction "Pin_18")
 			(pintype "passive")
 			(uuid "1ce81493-aebb-438d-84a3-9def668e9ccc")
@@ -3497,7 +3707,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 50 "Net-(J3-Pin_20)")
+			(net 50 "/D7")
 			(pinfunction "Pin_20")
 			(pintype "passive")
 			(uuid "1d11d1f2-90f9-4010-9f6b-d7807f9e2d19")
@@ -3519,7 +3729,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 51 "Net-(J3-Pin_22)")
+			(net 51 "/RS0")
 			(pinfunction "Pin_22")
 			(pintype "passive")
 			(uuid "1e483c89-82eb-4ddd-bdca-bb51e1c7a556")
@@ -3541,7 +3751,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 52 "Net-(J3-Pin_24)")
+			(net 59 "/RS1")
 			(pinfunction "Pin_24")
 			(pintype "passive")
 			(uuid "eaa8ade5-4511-4525-9cf1-0cd59eb0df20")
@@ -3563,7 +3773,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 53 "Net-(J3-Pin_26)")
+			(net 54 "/RS2")
 			(pinfunction "Pin_26")
 			(pintype "passive")
 			(uuid "5dbae36c-3499-4f00-8004-76072181bb0c")
@@ -3790,6 +4000,490 @@
 			)
 		)
 	)
+	(footprint "Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder"
+		(layer "F.Cu")
+		(uuid "c16099ec-7e5b-4cf1-8f7e-6c641d3b4cbc")
+		(at 182.4 65.4)
+		(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal with elongated pad for handsoldering. (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "capacitor handsolder")
+		(property "Reference" "C5"
+			(at 0 -1.43 360)
+			(layer "F.SilkS")
+			(uuid "f607c461-0004-4b4a-b577-146a504f0136")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "C"
+			(at 0 1.43 360)
+			(layer "F.Fab")
+			(uuid "23fd563f-fd66-4492-bf25-a2f676111b83")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Footprint" "Capacitor_SMD:C_0603_1608Metric_Pad1.08x0.95mm_HandSolder"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "905b6c98-85c2-4c9b-a304-b256d7f02708")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Datasheet" ""
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "9bb4333e-8cb8-4f48-b10d-2b04118e85d5")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property "Description" "Unpolarized capacitor"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "169cd386-7d8d-43b2-8680-f5741fd2c7d4")
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+			)
+		)
+		(property ki_fp_filters "C_*")
+		(path "/8ee85f30-2ff5-4f46-8395-020eead74df9")
+		(sheetname "Root")
+		(sheetfile "bt475-interface.kicad_sch")
+		(attr smd)
+		(fp_line
+			(start -0.146267 -0.51)
+			(end 0.146267 -0.51)
+			(stroke
+				(width 0.12)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "7eda02d8-67e4-4558-a6f9-b6b1270bb647")
+		)
+		(fp_line
+			(start -0.146267 0.51)
+			(end 0.146267 0.51)
+			(stroke
+				(width 0.12)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "226c58a5-12ad-40dc-bfce-8bf3eb0c5276")
+		)
+		(fp_line
+			(start -1.65 -0.73)
+			(end 1.65 -0.73)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "F.CrtYd")
+			(uuid "93955002-4b69-4c0a-ae31-4a26ba5d9e6f")
+		)
+		(fp_line
+			(start -1.65 0.73)
+			(end -1.65 -0.73)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "F.CrtYd")
+			(uuid "3b1836cb-0f1e-4e6b-ab36-4b9870b86491")
+		)
+		(fp_line
+			(start 1.65 -0.73)
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@@ -8290,24 +9492,24 @@
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diff --git a/pcbs/bt475-interface/bt475-interface.kicad_pro b/pcbs/bt475-interface/bt475-interface.kicad_pro
index 486e893..5ad9900 100644
--- a/pcbs/bt475-interface/bt475-interface.kicad_pro
+++ b/pcbs/bt475-interface/bt475-interface.kicad_pro
@@ -229,7 +229,11 @@
     "equivalence_files": []
   },
   "erc": {
-    "erc_exclusions": [],
+    "erc_exclusions": [
+      "pin_to_pin|1549400|1130300|f1ece11b-a229-42d6-b8d9-e548445ebaaf|7fe1f6b7-18a0-435d-ab9c-6f1fedd35fe7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7",
+      "pin_to_pin|1549400|1181100|7847301a-d3eb-40f9-961d-afac2d36ac79|7fe1f6b7-18a0-435d-ab9c-6f1fedd35fe7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7",
+      "pin_to_pin|1549400|1206500|96865382-31dc-46ad-83a0-c660a9decdc3|7fe1f6b7-18a0-435d-ab9c-6f1fedd35fe7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7|/0464b11d-1301-49ff-b9e8-86e5551d8ba7"
+    ],
     "meta": {
       "version": 0
     },
diff --git a/pcbs/bt475-interface/bt475-interface.kicad_sch b/pcbs/bt475-interface/bt475-interface.kicad_sch
index f35b3b5..a00f85c 100644
--- a/pcbs/bt475-interface/bt475-interface.kicad_sch
+++ b/pcbs/bt475-interface/bt475-interface.kicad_sch
@@ -2035,6 +2035,142 @@
 				)
 			)
 		)
+		(symbol "Regulator_Linear:AMS1117-3.3"
+			(exclude_from_sim no)
+			(in_bom yes)
+			(on_board yes)
+			(property "Reference" "U"
+				(at -3.81 3.175 0)
+				(effects
+					(font
+						(size 1.27 1.27)
+					)
+				)
+			)
+			(property "Value" "AMS1117-3.3"
+				(at 0 3.175 0)
+				(effects
+					(font
+						(size 1.27 1.27)
+					)
+					(justify left)
+				)
+			)
+			(property "Footprint" "Package_TO_SOT_SMD:SOT-223-3_TabPin2"
+				(at 0 5.08 0)
+				(effects
+					(font
+						(size 1.27 1.27)
+					)
+					(hide yes)
+				)
+			)
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@@ -7294,6 +7598,72 @@
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@@ -7506,6 +7876,76 @@
 		)
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 		(lib_id "power:GND")
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@@ -7572,6 +8012,72 @@
 		)
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@@ -8288,6 +8794,76 @@
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 		(lib_id "power:GND")
 		(at 233.68 97.79 0)
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@@ -8559,6 +9135,72 @@
 	)
 	(symbol
 		(lib_id "power:GND")
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 		(unit 1)
 		(exclude_from_sim no)
@@ -8624,6 +9266,77 @@
 		)
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+		(property "Datasheet" "http://www.advanced-monolithic.com/pdf/ds1117.pdf"
+			(at 53.34 163.83 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(property "Description" "1A Low Dropout regulator, positive, 3.3V fixed output, SOT-223"
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+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
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+		(pin "1"
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+		)
+		(pin "3"
+			(uuid "7c49c395-9dd4-42d0-9118-4952423744dc")
+		)
+		(pin "2"
+			(uuid "75594c6e-9c82-4294-a690-6435fac86bf2")
+		)
+		(instances
+			(project "bt475-interface"
+				(path "/0464b11d-1301-49ff-b9e8-86e5551d8ba7"
+					(reference "U5")
+					(unit 1)
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+	)
+	(symbol
 		(lib_id "power:+5V")
 		(at 152.4 40.64 0)
 		(unit 1)
@@ -9357,6 +10070,72 @@
 		)
 	)
 	(symbol
+		(lib_id "power:GND")
+		(at 40.64 170.18 0)
+		(unit 1)
+		(exclude_from_sim no)
+		(in_bom yes)
+		(on_board yes)
+		(dnp no)
+		(fields_autoplaced yes)
+		(uuid "ea49704d-c3e2-48d3-9f3a-03319fb35cfd")
+		(property "Reference" "#PWR036"
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+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(property "Value" "GND"
+			(at 40.64 174.3131 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
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+		)
+		(property "Footprint" ""
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+			(effects
+				(font
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+				)
+				(hide yes)
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+			(effects
+				(font
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+				(hide yes)
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+		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
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+			(effects
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+			(project "bt475-interface"
+				(path "/0464b11d-1301-49ff-b9e8-86e5551d8ba7"
+					(reference "#PWR036")
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+	)
+	(symbol
 		(lib_id "Device:C")
 		(at 44.45 54.61 0)
 		(unit 1)