working 4 bit fb

7 files changed, 60 insertions, 22 deletions

diff --git a/fpga/hp_lcd_driver/Makefile b/fpga/hp_lcd_driver/Makefile
index 0558bdd..6e21f21 100644
--- a/fpga/hp_lcd_driver/Makefile
+++ b/fpga/hp_lcd_driver/Makefile
@@ -7,7 +7,7 @@ TARGETS=ebaz4205
 
 better_default: ${TARGETS:%=build_%/hp_lcd_driver.svf}
 	scp build_ebaz4205/out/hp_lcd_driver.bin ${DIP}:/boot/uboot/hp_lcd_driver.bin
-	ssh -n ${DIP} reboot < /dev/null & 
+	#ssh -n ${DIP} reboot < /dev/null & 
 
 qbetter_default: build_rando_a7/hp_lcd_driver.svf
 	./prog_a7
diff --git a/fpga/hp_lcd_driver/common.vhdl b/fpga/hp_lcd_driver/common.vhdl
index 39d1f28..a3e41d4 100644
--- a/fpga/hp_lcd_driver/common.vhdl
+++ b/fpga/hp_lcd_driver/common.vhdl
@@ -46,7 +46,10 @@ entity common is
           video_out_index : out std_logic;
 	  video_in_addr   : out std_logic_vector(addr_width-1 downto 0);
 	  video_in_clk    : out std_logic;
-	  video_in_data   : in std_logic_vector(1 downto 0)
+	  video_in_gate   : in std_logic;
+	  video_in_r   : in std_logic_vector(7 downto 0);
+	  video_in_g   : in std_logic_vector(7 downto 0);
+	  video_in_b   : in std_logic_vector(7 downto 0)
           );
 
 end common;
@@ -264,15 +267,12 @@ begin
 
 
 
-    r <= r_s when video_in_data(1) = '0' else
-	x"00" when video_in_data(0)='0' else
-	x"ff";
-    g <= g_s when video_in_data(1) = '0' else
-	x"00" when video_in_data(0)='0' else
-	x"ff";
-    b <= b_s when video_in_data(1) = '0' else
-	x"00" when video_in_data(0)='0' else
-	x"ff";
+    r <= r_s when video_in_gate = '0' else
+	video_in_r;
+    g <= g_s when video_in_gate = '0' else
+	video_in_g;
+    b <= b_s when video_in_gate = '0' else
+	video_in_b;
 
     output0 : entity work.output_stage
 
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
index d68afa5..5c29ff6 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -77,7 +77,10 @@ begin
                   video_out_valid => open,
 		  video_in_clk    => open,
 		  video_in_addr   => open,
-		  video_in_data   => x"00"
+		  video_in_gate   => '0',
+		  video_in_r => open,
+		  video_in_g => open,
+		  video_in_b => open
                   );
 end Behavioral;
 
diff --git a/fpga/hp_lcd_driver/output_stage.vhdl b/fpga/hp_lcd_driver/output_stage.vhdl
index 234d16d..4787dc6 100644
--- a/fpga/hp_lcd_driver/output_stage.vhdl
+++ b/fpga/hp_lcd_driver/output_stage.vhdl
@@ -137,7 +137,7 @@ begin
             o   => grid_d
             );
 
-    r <= r_in when grid_d='0' else x"ff";
+    r <= r_in; -- when grid_d='0' else x"ff";
     g <= g_in;
     b <= b_in;
 
diff --git a/fpga/hp_lcd_driver/zynq7.mk b/fpga/hp_lcd_driver/zynq7.mk
index 1426f38..05f5727 100644
--- a/fpga/hp_lcd_driver/zynq7.mk
+++ b/fpga/hp_lcd_driver/zynq7.mk
@@ -35,7 +35,6 @@ SRCS= ${IP} \
 	tmds_output_artix7.vhdl \
 	tmds_phy_artix7.vhdl \
 	vram_artix7.vhdl \
-	overlay_vram_artix7.vhdl \
 	zynq7_wrapper.vhdl \
 	fifo_to_axi.vhdl \
 	vnc_serializer.vhdl 
diff --git a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
index e178395..588d624 100644
--- a/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
+++ b/fpga/hp_lcd_driver/zynq7_ip/blk_mem_gen_1.tcl
@@ -13,7 +13,7 @@ set_property -dict [list  \
 	CONFIG.Use_Byte_Write_Enable {true}  \
 	CONFIG.Byte_Size {8}  \
 	CONFIG.Write_Width_A {32}  \
-	CONFIG.Write_Depth_A {16384}  \
+	CONFIG.Write_Depth_A {28800}  \
 	CONFIG.Read_Width_A {32}  \
 	CONFIG.Operating_Mode_A {WRITE_FIRST}  \
 	CONFIG.Write_Width_B {32}  \
diff --git a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
index ca90bea..0e7367e 100644
--- a/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
+++ b/fpga/hp_lcd_driver/zynq7_wrapper.vhdl
@@ -100,6 +100,21 @@ end entity zynq7_wrapper;
 
 architecture arch of zynq7_wrapper is
 
+    type t_palette is array (0 to 15) of std_logic_vector(7 downto 0);  
+    constant r_lut : t_palette := (
+		x"00", x"00", x"00", x"00", x"AA", x"AA", x"AA", x"AA",
+		x"55", x"55", x"55", x"55", x"FF", x"FF", x"FF", x"FF"
+    );
+    constant g_lut : t_palette := (
+		x"00", x"00", x"AA", x"AA", x"00", x"00", x"55", x"AA",
+		x"55", x"55", x"FF", x"FF", x"55", x"55", x"FF", x"FF"
+    );
+    constant b_lut : t_palette := (
+		x"00", x"AA", x"00", x"AA", x"00", x"AA", x"00", x"AA",
+		x"55", x"FF", x"55", x"FF", x"55", x"FF", x"55", x"FF"
+    );
+
+
     signal eth0_gmii_txd : std_logic_vector(7 downto 0);
     signal eth0_gmii_rxd : std_logic_vector(7 downto 0);
 
@@ -193,8 +208,13 @@ architecture arch of zynq7_wrapper is
 
     signal overlay_addr : std_logic_vector(addr_width-1 downto 0);
     signal overlay_clk  : std_logic;
-    signal overlay_data : std_logic_vector(1 downto 0);
+    signal overlay_demux_p :integer;
     signal overlay_demux :integer;
+    signal overlay_data : integer;
+    signal overlay_gate  : std_logic;
+    signal overlay_r  : std_logic_vector(7 downto 0);
+    signal overlay_g  : std_logic_vector(7 downto 0);
+    signal overlay_b  : std_logic_vector(7 downto 0);
 
 
     signal fb_ps_clk : STD_LOGIC;
@@ -204,9 +224,11 @@ architecture arch of zynq7_wrapper is
     signal fb_ps_wrdata : STD_LOGIC_VECTOR ( 31 downto 0 );
     signal fb_ps_rddata : STD_LOGIC_VECTOR ( 31 downto 0 );
 
-    signal fb_pl_addr : STD_LOGIC_VECTOR ( 13 downto 0 );
+    signal fb_pl_addr : STD_LOGIC_VECTOR ( 14 downto 0 );
     signal fb_pl_rddata : STD_LOGIC_VECTOR ( 31 downto 0 );
 
+    
+
 begin
 
     scope_ch1 <= gp0_awvalid; --clk_50m_ps;
@@ -250,7 +272,10 @@ begin
                   video_out_index => vnc_index,
 		  video_in_clk    => overlay_clk,
 		  video_in_addr   => overlay_addr,
-		  video_in_data   => overlay_data
+		  video_in_gate   => overlay_gate,
+		  video_in_r   => overlay_r,
+		  video_in_g   => overlay_g,
+		  video_in_b   => overlay_b
                   );
 
     processing_system7_0_i : entity work.processing_system7_0
@@ -475,11 +500,22 @@ begin
 
 
 
-	fb_pl_addr <= overlay_addr(17 downto 4);
+	fb_pl_addr <= overlay_addr(17 downto 3);
         
-   overlay_demux <= to_integer(unsigned(overlay_addr(3 downto 0)))*2;
-   overlay_data(0) <= fb_pl_rddata(overlay_demux);
-   overlay_data(1) <= fb_pl_rddata(overlay_demux +1);
+   process (overlay_clk) begin
+	if rising_edge(overlay_clk) then
+   		overlay_demux_p <= to_integer(unsigned(overlay_addr(2 downto 0)))*4;
+   		overlay_demux <=overlay_demux_p;
+	end if;
+   end process;
+
+   overlay_data <= to_integer(unsigned(fb_pl_rddata(overlay_demux+3 downto overlay_demux)));
+
+   overlay_gate <= '0' when overlay_data = 0 else '1';
+   overlay_r <= r_lut(overlay_data);
+   overlay_g <= g_lut(overlay_data);
+   overlay_b <= b_lut(overlay_data);
+
 
      -- fb_ps_rddata <=x"9abcdef0";