update spartan6 to match clocking from smh-ac415

2 files changed, 33 insertions, 13 deletions

diff --git a/fpga/hp_lcd_driver/clkgen_spartan6.vhdl b/fpga/hp_lcd_driver/clkgen_spartan6.vhdl
index 7240abc..555ef9e 100644
--- a/fpga/hp_lcd_driver/clkgen_spartan6.vhdl
+++ b/fpga/hp_lcd_driver/clkgen_spartan6.vhdl
@@ -19,17 +19,37 @@ entity clkgen is
 end clkgen;
 architecture Behavioural of clkgen is
 
-    signal clkfbout   : std_logic;
+    signal clkfbout1   : std_logic;
+    signal clkfbout2   : std_logic;
     signal clk_200m   : std_logic;
     signal clk_80m    : std_logic;
+    signal clk_78_571m    : std_logic;
     signal clk_40m    : std_logic;
     signal clk_20m    : std_logic;
-    signal pll_locked : std_logic;
+    signal pll_locked1 : std_logic;
+    signal pll_locked2 : std_logic;
 
-    signal reset : std_logic;
+    signal reset1 : std_logic;
+    signal reset2 : std_logic;
 begin
 
-    pll : PLL_BASE generic map (
+    pll1 : PLL_BASE generic map (
+        CLKIN_PERIOD   => 20.0,
+        CLKFBOUT_MULT  => 11,
+        CLKOUT0_DIVIDE => 7,
+        COMPENSATION   => "INTERNAL")
+        port map (
+            CLKFBOUT => clkfbout1,
+            CLKOUT0  => clk_78_571m,
+            CLKFBIN  => clkfbout1,
+            CLKIN    => clk_in,
+            LOCKED   => pll_locked1,
+            RST      => reset1);
+
+    reset1 <= (not pll_locked1) or (not sys_rst_n);
+
+
+    pll2 : PLL_BASE generic map (
         CLKIN_PERIOD   => 20.0,
         CLKFBOUT_MULT  => 8,
         CLKOUT0_DIVIDE => 2,
@@ -38,17 +58,17 @@ begin
         CLKOUT3_DIVIDE => 20,
         COMPENSATION   => "INTERNAL")
         port map (
-            CLKFBOUT => clkfbout,
+            CLKFBOUT => clkfbout2,
             CLKOUT0  => clk_200m,
-            CLKOUT1  => clk_80m,
+            CLKOUT1  => open,
             CLKOUT2  => clk_40m,
             CLKOUT3  => clk_20m,
-            LOCKED   => pll_locked,
-            CLKFBIN  => clkfbout,
+            LOCKED   => pll_locked2,
+            CLKFBIN  => clkfbout2,
             CLKIN    => clk_in,
-            RST      => reset);
+            RST      => reset2);
 
-    reset <= (not pll_locked) or (not sys_rst_n);
+    reset2 <= (not pll_locked2) or (not sys_rst_n);
 
 
 
@@ -63,11 +83,11 @@ begin
 
 
     i_clk_buf : BUFG port map (
-        I => clk_80m,
+        I => clk_78_571m,
         O => i_clk);
 
     o_clk_phy <= clk_200m;
 
-    locked <= pll_locked;
+    locked <= pll_locked2;
 
 end Behavioural;
diff --git a/fpga/hp_lcd_driver/hp_lcd_driver.ucf b/fpga/hp_lcd_driver/hp_lcd_driver.ucf
index ae00a1b..949bee4 100644
--- a/fpga/hp_lcd_driver/hp_lcd_driver.ucf
+++ b/fpga/hp_lcd_driver/hp_lcd_driver.ucf
@@ -14,7 +14,7 @@ NET "hsync_out" IOSTANDARD = LVCMOS33;
 NET "vsync_out" IOSTANDARD = LVCMOS33;
 
 
-INST "clkgen/pll" LOC = PLL_ADV_X0Y1;
+INST "clkgen/pll2" LOC = PLL_ADV_X0Y1;
 INST "output0/tmds_o/ioclk_buf" LOC = BUFPLL_X1Y5;
 
 NET "hdmi_c_p" LOC = P144;