tidy

8 files changed, 457 insertions, 455 deletions

diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index 85e04e3..ba0c460 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -36,24 +36,24 @@ use UNISIM.vcomponents.all;
 entity hp_lcd_driver is
     generic (video_width : natural := 2;
              addr_width  : natural := 18);
-    port (clk_50m : in  std_logic;
-          sys_rst_n  : in  std_logic;
-          video      : in  std_logic_vector(video_width-1 downto 0);
-          hsync_in   : in  std_logic;
-          vsync_in   : in  std_logic;
-          r_out    : out std_logic;
-          b_out   : out std_logic;
-          g_out  : out std_logic;
-          hsync_out  : out std_logic;
-          vsync_out  : out std_logic;
-            hdmi_c_p : out std_logic;
-            hdmi_c_n : out std_logic;
-            hdmi_r_p : out std_logic;
-            hdmi_r_n : out std_logic;
-            hdmi_g_p : out std_logic;
-            hdmi_g_n : out std_logic;
-            hdmi_b_p : out std_logic;
-            hdmi_b_n : out std_logic);
+    port (clk_50m   : in  std_logic;
+          sys_rst_n : in  std_logic;
+          video     : in  std_logic_vector(video_width-1 downto 0);
+          hsync_in  : in  std_logic;
+          vsync_in  : in  std_logic;
+          r_out     : out std_logic;
+          b_out     : out std_logic;
+          g_out     : out std_logic;
+          hsync_out : out std_logic;
+          vsync_out : out std_logic;
+          hdmi_c_p  : out std_logic;
+          hdmi_c_n  : out std_logic;
+          hdmi_r_p  : out std_logic;
+          hdmi_r_n  : out std_logic;
+          hdmi_g_p  : out std_logic;
+          hdmi_g_n  : out std_logic;
+          hdmi_b_p  : out std_logic;
+          hdmi_b_n  : out std_logic);
 
 end hp_lcd_driver;
 
@@ -66,26 +66,26 @@ architecture Behavioral of hp_lcd_driver is
     signal rd_addr : std_logic_vector(addr_width-1 downto 0);
     signal rd_data : std_logic_vector(video_width-1 downto 0);
 
-    signal r  : std_logic_vector(7 downto 0);
+    signal r : std_logic_vector(7 downto 0);
     signal g : std_logic_vector(7 downto 0);
-    signal b  : std_logic_vector(7 downto 0);
+    signal b : std_logic_vector(7 downto 0);
 
 
-    signal i_clk   : std_logic;
+    signal i_clk : std_logic;
 
-    signal o_clk_locked   : std_logic;
-    signal o_clk   : std_logic;
-    signal o_clk_x2   : std_logic;
-    signal o_clk_x10   : std_logic;
+    signal o_clk_locked : std_logic;
+    signal o_clk        : std_logic;
+    signal o_clk_x2     : std_logic;
+    signal o_clk_x10    : std_logic;
     signal serdesstrobe : std_logic;
 
-    signal clkfbout:std_logic;
-    signal clk_200m:std_logic;
-    signal clk_80m:std_logic;
-    signal clk_40m:std_logic;
-    signal clk_20m:std_logic;
-    signal pll_locked:std_logic;
-    signal pll_locked_n:std_logic;
+    signal clkfbout     : std_logic;
+    signal clk_200m     : std_logic;
+    signal clk_80m      : std_logic;
+    signal clk_40m      : std_logic;
+    signal clk_20m      : std_logic;
+    signal pll_locked   : std_logic;
+    signal pll_locked_n : std_logic;
 
     signal sys_rst : std_logic;
 
@@ -95,52 +95,52 @@ begin
 
 
 
-pll: PLL_BASE generic map (
-	CLKIN_PERIOD=>20.0,
-	CLKFBOUT_MULT => 8,
-	CLKOUT0_DIVIDE => 2,
-	CLKOUT1_DIVIDE => 5,
-	CLKOUT2_DIVIDE => 10,
-	CLKOUT3_DIVIDE => 20,
-	COMPENSATION => "INTERNAL")
-	port map (
-	CLKFBOUT => clkfbout,
-	CLKOUT0 => clk_200m,
-	CLKOUT1 => clk_80m,
-	CLKOUT2 => clk_40m,
-	CLKOUT3 => clk_20m,
-	LOCKED => pll_locked,
-	CLKFBIN => clkfbout,
-	CLKIN => clk_50m,
-	RST => pll_locked_n);
+    pll : PLL_BASE generic map (
+        CLKIN_PERIOD   => 20.0,
+        CLKFBOUT_MULT  => 8,
+        CLKOUT0_DIVIDE => 2,
+        CLKOUT1_DIVIDE => 5,
+        CLKOUT2_DIVIDE => 10,
+        CLKOUT3_DIVIDE => 20,
+        COMPENSATION   => "INTERNAL")
+        port map (
+            CLKFBOUT => clkfbout,
+            CLKOUT0  => clk_200m,
+            CLKOUT1  => clk_80m,
+            CLKOUT2  => clk_40m,
+            CLKOUT3  => clk_20m,
+            LOCKED   => pll_locked,
+            CLKFBIN  => clkfbout,
+            CLKIN    => clk_50m,
+            RST      => pll_locked_n);
+
+    pll_locked_n <= not pll_locked;
 
-pll_locked_n <= not pll_locked;
 
 
 
+    ioclk_buf : BUFPLL generic map (DIVIDE => 5)
+        port map (
+            PLLIN        => clk_200m,
+            GCLK         => o_clk_x2,
+            LOCKED       => pll_locked,
+            IOCLK        => o_clk_x10,
+            SERDESSTROBE => serdesstrobe,
+            LOCK         => o_clk_locked);
+
+    o_clk_buf : BUFG port map (
+        I =>clk_20m,
+        O =>o_clk);
 
-ioclk_buf: BUFPLL generic map ( DIVIDE=>5)
-	port map (
-		PLLIN=>clk_200m,
-		GCLK=>o_clk_x2,
-		LOCKED => pll_locked,
-		IOCLK => o_clk_x10,
-		SERDESSTROBE => serdesstrobe,
-		LOCK => o_clk_locked);
 
-o_clk_buf: BUFG port map (
-	I=>clk_20m,
-	O=>o_clk);
+    o_clk_x2_buf : BUFG port map (
+        I =>clk_40m,
+        O =>o_clk_x2);
 
-	
-o_clk_x2_buf: BUFG port map (
-	I=>clk_40m,
-	O=>o_clk_x2);
 
-	
-i_clk_buf: BUFG port map (
-	I=>clk_80m,
-	O=>i_clk);
+    i_clk_buf : BUFG port map (
+        I =>clk_80m,
+        O =>i_clk);
 
 
 
@@ -180,14 +180,14 @@ i_clk_buf: BUFG port map (
             );
 
 
-    r<= x"ff" when  rd_data(1)='1' else
-	x"00";
-    g<= x"ff" when  rd_data(0)='1' else
-	x"ff" when rd_data(1)='1' else
-	x"00";
-    b<= x"ff" when  rd_data(1)='1' else
-	x"00";
-	
+    r <= x"ff" when rd_data(1) = '1' else
+        x"00";
+    g <= x"ff" when rd_data(0) = '1' else
+        x"ff" when rd_data(1) = '1' else
+        x"00";
+    b <= x"ff" when rd_data(1) = '1' else
+        x"00";
+
 
 
     output0 : entity work.output_stage
@@ -207,30 +207,30 @@ i_clk_buf: BUFG port map (
             v_stride     => 384
             )
         port map(
-	    clk_locked => o_clk_locked,
-            clk       => o_clk,
-	    clk_x2	=> o_clk_x2,		
-	    clk_x10	=> o_clk_x10,		
-	    serdesstrobe => serdesstrobe,
-            sys_rst_n => sys_rst_n,
-            vsync_in  => vsync_in,
-            r_in    => r,
-            g_in  => g,
-            b_in   => b,
-            addr_out  => rd_addr,
-            r_out   => r_out,
-            g_out => g_out,
-            b_out  => b_out,
-            hsync_out => hsync_out,
-            vsync_out => vsync_out,
-hdmi_c_p=> hdmi_c_p,
-hdmi_c_n=> hdmi_c_n,
-hdmi_r_p=> hdmi_r_p,
-hdmi_r_n=> hdmi_r_n,
-hdmi_g_p=> hdmi_g_p,
-hdmi_g_n=> hdmi_g_n,
-hdmi_b_p=> hdmi_b_p,
-hdmi_b_n=> hdmi_b_n
+            clk_locked   => o_clk_locked,
+            clk          => o_clk,
+            clk_x2       => o_clk_x2,
+            clk_x10      => o_clk_x10,
+            serdesstrobe => serdesstrobe,
+            sys_rst_n    => sys_rst_n,
+            vsync_in     => vsync_in,
+            r_in         => r,
+            g_in         => g,
+            b_in         => b,
+            addr_out     => rd_addr,
+            r_out        => r_out,
+            g_out        => g_out,
+            b_out        => b_out,
+            hsync_out    => hsync_out,
+            vsync_out    => vsync_out,
+            hdmi_c_p     => hdmi_c_p,
+            hdmi_c_n     => hdmi_c_n,
+            hdmi_r_p     => hdmi_r_p,
+            hdmi_r_n     => hdmi_r_n,
+            hdmi_g_p     => hdmi_g_p,
+            hdmi_g_n     => hdmi_g_n,
+            hdmi_b_p     => hdmi_b_p,
+            hdmi_b_n     => hdmi_b_n
             );
 
 
diff --git a/spartan6/hp_lcd_driver/output_analog.vhdl b/spartan6/hp_lcd_driver/output_analog.vhdl
index 29870cf..af9eb71 100644
--- a/spartan6/hp_lcd_driver/output_analog.vhdl
+++ b/spartan6/hp_lcd_driver/output_analog.vhdl
@@ -9,16 +9,16 @@ entity output_analog is
             clk       : in std_logic;
             sys_rst_n : in std_logic;
 
-            r_in   : in std_logic;
-            g_in : in std_logic;
-            b_in  : in std_logic;
+            r_in     : in std_logic;
+            g_in     : in std_logic;
+            b_in     : in std_logic;
             hsync_in : in std_logic;
             vsync_in : in std_logic;
             blank_in : in std_logic;
 
-            r_out   : out std_logic;
-            g_out : out std_logic;
-            b_out  : out std_logic;
+            r_out     : out std_logic;
+            g_out     : out std_logic;
+            b_out     : out std_logic;
             hsync_out : out std_logic;
             vsync_out : out std_logic
             );
@@ -28,9 +28,9 @@ end output_analog;
 architecture beh of output_analog is
 
 
-    signal r_r   : std_logic;
+    signal r_r : std_logic;
     signal g_r : std_logic;
-    signal b_r  : std_logic;
+    signal b_r : std_logic;
 
     signal hsync_r : std_logic;
     signal vsync_r : std_logic;
@@ -43,16 +43,16 @@ begin
     process (sys_rst_n, clk)
     begin
         if sys_rst_n = '0' then
-            r_r   <= '0';
-            g_r <= '0';
-            b_r  <= '0';
+            r_r     <= '0';
+            g_r     <= '0';
+            b_r     <= '0';
             hsync_r <= '0';
             vsync_r <= '0';
             blank_r <= '0';
         elsif rising_edge(clk) then
-            r_r   <= r_in;
-            g_r <= g_in;
-            b_r  <= b_in;
+            r_r     <= r_in;
+            g_r     <= g_in;
+            b_r     <= b_in;
             hsync_r <= hsync_in;
             vsync_r <= vsync_in;
             blank_r <= blank_in;
@@ -64,15 +64,15 @@ begin
     process (sys_rst_n, clk)
     begin
         if sys_rst_n = '0' then
-            r_out   <= '0';
-            g_out <= '0';
-            b_out  <= '0';
+            r_out     <= '0';
+            g_out     <= '0';
+            b_out     <= '0';
             hsync_out <= '0';
             vsync_out <= '0';
         elsif rising_edge(clk) then
-            r_out   <= r_r and not blank_r;
-            g_out <= g_r and not blank_r;
-            b_out  <= b_r and not blank_r;
+            r_out     <= r_r and not blank_r;
+            g_out     <= g_r and not blank_r;
+            b_out     <= b_r and not blank_r;
             hsync_out <= hsync_r;
             vsync_out <= vsync_r;
         end if;
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
index 839fb6d..4f35e35 100644
--- a/spartan6/hp_lcd_driver/output_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -58,18 +58,18 @@ begin
     process (clk, vsync_in_ne, sys_rst_n)
     begin
         if sys_rst_n = '0' then
-            h <=0;
-            v <=0;
+            h <= 0;
+            v <= 0;
         elsif rising_edge(clk) then
             if h /= (h_total-1) then
-                h <=h+1;
+                h <= h+1;
             else
                 if v /= (v_total-1) then
-                    v <=v+1;
-                    h <=0;
+                    v <= v+1;
+                    h <= 0;
                 elsif vsync_in_ne = '1' then
-                    h <=0;
-                    v <=0;
+                    h <= 0;
+                    v <= 0;
                 end if;
             end if;
         end if;
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index 8a8ab44..d4b3d9f 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -24,25 +24,25 @@ entity output_stage is
              );
     port
         (
-            clk_locked       : in std_logic;
-            clk       : in std_logic;
+            clk_locked   : in std_logic;
+            clk          : in std_logic;
             clk_x2       : in std_logic;
-            clk_x10       : in std_logic;
-            serdesstrobe       : in std_logic;
-            sys_rst_n : in std_logic;
+            clk_x10      : in std_logic;
+            serdesstrobe : in std_logic;
+            sys_rst_n    : in std_logic;
 
             vsync_in : in std_logic;
 
             addr_out : out std_logic_vector(addr_width - 1 downto 0);
 
-            r_in   : in std_logic_vector(7 downto 0);
+            r_in : in std_logic_vector(7 downto 0);
             g_in : in std_logic_vector(7 downto 0);
-            b_in  : in std_logic_vector(7 downto 0);
+            b_in : in std_logic_vector(7 downto 0);
 
 
-            r_out   : out std_logic;
-            g_out : out std_logic;
-            b_out  : out std_logic;
+            r_out     : out std_logic;
+            g_out     : out std_logic;
+            b_out     : out std_logic;
             hsync_out : out std_logic;
             vsync_out : out std_logic;
 
@@ -121,49 +121,49 @@ begin
         port map(
             sys_rst_n => sys_rst_n,
 
-            clk       => clk,
+            clk => clk,
 
             hsync_in => hsync,
             vsync_in => vsync,
             blank_in => blank,
-            r_in   => g_in(7),
-            g_in => g_in(6),
-            b_in  => b_in(7),
+            r_in     => g_in(7),
+            g_in     => g_in(6),
+            b_in     => b_in(7),
 
-            r_out   => r_out,
-            g_out => g_out,
-            b_out  => b_out,
+            r_out     => r_out,
+            g_out     => g_out,
+            b_out     => b_out,
             hsync_out => hsync_out,
             vsync_out => vsync_out
             );
 
 
 
-output_tmds: entity work.tmds_output 
-	port map (
-            sys_rst_n => sys_rst_n,
-	    pclk_locked => clk_locked,
-            pclk       => clk,
-            pclk_x2       => clk_x2,
-            pclk_x10       => clk_x10,
-	    serdesstrobe => serdesstrobe,
-
-		r_in => r_in,
-		g_in => g_in,
-		b_in => b_in,
-		hsync => hsync,
-		vsync => vsync,
-		blank => blank,
-
-	tmds_c_out_p => hdmi_c_p,
-	tmds_c_out_n => hdmi_c_n,
-	tmds_r_out_p => hdmi_r_p,
-	tmds_r_out_n => hdmi_r_n,
-	tmds_g_out_p => hdmi_g_p,
-	tmds_g_out_n => hdmi_g_n,
-	tmds_b_out_p => hdmi_b_p,
-	tmds_b_out_n => hdmi_b_n
-);
+    output_tmds : entity work.tmds_output
+        port map (
+            sys_rst_n    => sys_rst_n,
+            pclk_locked  => clk_locked,
+            pclk         => clk,
+            pclk_x2      => clk_x2,
+            pclk_x10     => clk_x10,
+            serdesstrobe => serdesstrobe,
+
+            r_in  => r_in,
+            g_in  => g_in,
+            b_in  => b_in,
+            hsync => hsync,
+            vsync => vsync,
+            blank => blank,
+
+            tmds_c_out_p => hdmi_c_p,
+            tmds_c_out_n => hdmi_c_n,
+            tmds_r_out_p => hdmi_r_p,
+            tmds_r_out_n => hdmi_r_n,
+            tmds_g_out_p => hdmi_g_p,
+            tmds_g_out_n => hdmi_g_n,
+            tmds_b_out_p => hdmi_b_p,
+            tmds_b_out_n => hdmi_b_n
+            );
 
 
 
diff --git a/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl b/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl
index dccf6af..dec3c9a 100644
--- a/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl
+++ b/spartan6/hp_lcd_driver/serdes_n_to_1.vhdl
@@ -7,112 +7,112 @@ use UNISIM.vcomponents.all;
 
 
 entity serdes_n_to_1 is
-	generic (
-	  SF : natural :=8
-	);
-	port (
-	
-ioclk: in std_logic;
-serdesstrobe: in std_logic;
-reset : in std_logic;
-gclk : in std_logic;
-datain : in std_logic_vector(SF-1 downto 0);
-iob_data_out : out std_logic
-);
+    generic (
+        SF : natural := 8
+        );
+    port (
+
+        ioclk        : in  std_logic;
+        serdesstrobe : in  std_logic;
+        reset        : in  std_logic;
+        gclk         : in  std_logic;
+        datain       : in  std_logic_vector(SF-1 downto 0);
+        iob_data_out : out std_logic
+        );
 end serdes_n_to_1;
 
 
 architecture beh of serdes_n_to_1 is
 
-signal cascade_di:std_logic;
-signal cascade_do:std_logic;
-signal cascade_ti:std_logic;
-signal cascade_to:std_logic;
-signal mdatain:std_logic_vector(8 downto 0);
+    signal cascade_di : std_logic;
+    signal cascade_do : std_logic;
+    signal cascade_ti : std_logic;
+    signal cascade_to : std_logic;
+    signal mdatain    : std_logic_vector(8 downto 0);
 
-begin 
+begin
 
-datain_for_1 : for b in 0 to SF -1 generate
-	mdatain(b)<=datain(b);
-end generate;
+    datain_for_1 : for b in 0 to SF -1 generate
+        mdatain(b) <= datain(b);
+    end generate;
 
-datain_for_2 : for b in SF to 8 generate
-	mdatain(b)<='0';
-end generate;
+    datain_for_2 : for b in SF to 8 generate
+        mdatain(b) <= '0';
+    end generate;
 
 --   mdatain <= ( SF-1 downto 0 => datain, others =>'0');
 
-   oserdes_m  : OSERDES2
-	generic map (
-		DATA_WIDTH => SF,
-		DATA_RATE_OQ => "SDR",
-		DATA_RATE_OT => "SDR",
-		SERDES_MODE => "MASTER",
-		OUTPUT_MODE => "DIFFERENTIAL"
-	)
+    oserdes_m : OSERDES2
+        generic map (
+            DATA_WIDTH   => SF,
+            DATA_RATE_OQ => "SDR",
+            DATA_RATE_OT => "SDR",
+            SERDES_MODE  => "MASTER",
+            OUTPUT_MODE  => "DIFFERENTIAL"
+            )
         port map (
-	OQ => iob_data_out,
-	OCE => '1',
-	CLK0 => ioclk,
-	CLK1 => '0',
-	IOCE => serdesstrobe,
-	RST => reset,
-	CLKDIV => gclk,
-	D4 => mdatain(7),
-	D3 => mdatain(6),
-	D2 => mdatain(5),
-	D1 => mdatain(4),
---	TQ => ,
-	T1 => '0',
-	T2 => '0',
-	T3 => '0',
-	T4 => '0',
-	TRAIN => '0',
-	TCE => '1',
-	SHIFTIN1 => '1',			-- Dummy input in Master
-	SHIFTIN2 => '1',			-- Dummy input in Master
-	SHIFTIN3 => cascade_do,		-- Cascade output D data from slave
-	SHIFTIN4 => cascade_to,		-- Cascade output T data from slave
-	SHIFTOUT1 => cascade_di,		-- Cascade input D data to slave
-	SHIFTOUT2 => cascade_ti		-- Cascade input T data to slave
---	SHIFTOUT3 => ,			-- Dummy output in Master
---	SHIFTOUT4 => 			-- Dummy output in Master
-	);
+            OQ        => iob_data_out,
+            OCE       => '1',
+            CLK0      => ioclk,
+            CLK1      => '0',
+            IOCE      => serdesstrobe,
+            RST       => reset,
+            CLKDIV    => gclk,
+            D4        => mdatain(7),
+            D3        => mdatain(6),
+            D2        => mdatain(5),
+            D1        => mdatain(4),
+--      TQ => ,
+            T1        => '0',
+            T2        => '0',
+            T3        => '0',
+            T4        => '0',
+            TRAIN     => '0',
+            TCE       => '1',
+            SHIFTIN1  => '1',           -- Dummy input in Master
+            SHIFTIN2  => '1',           -- Dummy input in Master
+            SHIFTIN3  => cascade_do,    -- Cascade output D data from slave
+            SHIFTIN4  => cascade_to,    -- Cascade output T data from slave
+            SHIFTOUT1 => cascade_di,    -- Cascade input D data to slave
+            SHIFTOUT2 => cascade_ti     -- Cascade input T data to slave
+--      SHIFTOUT3 => ,                  -- Dummy output in Master
+--      SHIFTOUT4 =>                    -- Dummy output in Master
+            );
 
-   oserdes_s  : OSERDES2
-	generic map (
-	DATA_WIDTH=>SF, 			-- SERDES word width.  This should match the setting is BUFPLL
-	DATA_RATE_OQ=>"SDR", 		-- <SDR>, DDR
-	DATA_RATE_OT =>"SDR", 		-- <SDR>, DDR
-	SERDES_MODE   =>"SLAVE", 		-- <DEFAULT>, MASTER, SLAVE
-	OUTPUT_MODE =>"DIFFERENTIAL"
-	)
-	port map (
---	OQ => ,
-	OCE => '1',
-	CLK0 => ioclk,
-	CLK1 => '0',
-	IOCE => serdesstrobe,
-	RST => reset,
-	CLKDIV => gclk,
-	D4 => mdatain(3),
-	D3 => mdatain(2),
-	D2 => mdatain(1),
-	D1 => mdatain(0),
---	TQ => ,
-	T1 => '0',
-	T2 => '0',
-	T3 => '0',
-	T4 => '0',
-	TRAIN => '0',
-	TCE => '1',
-	SHIFTIN1 => cascade_di,		-- Cascade input D from Master
-	SHIFTIN2 => cascade_ti,		-- Cascade input T from Master
-	SHIFTIN3 => '1',			-- Dummy input in Slave
-	SHIFTIN4 => '1',			-- Dummy input in Slave
---	SHIFTOUT1 => ,			-- Dummy output in Slave
---	SHIFTOUT2 => ,			-- Dummy output in Slave
-	SHIFTOUT3 => cascade_do,   	-- Cascade output D data to Master
-	SHIFTOUT4 => cascade_to) ; 	-- Cascade output T data to Master
+    oserdes_s : OSERDES2
+        generic map (
+            DATA_WIDTH   => SF,  -- SERDES word width.  This should match the setting is BUFPLL
+            DATA_RATE_OQ => "SDR",      -- <SDR>, DDR
+            DATA_RATE_OT => "SDR",      -- <SDR>, DDR
+            SERDES_MODE  => "SLAVE",    -- <DEFAULT>, MASTER, SLAVE
+            OUTPUT_MODE  => "DIFFERENTIAL"
+            )
+        port map (
+--      OQ => ,
+            OCE       => '1',
+            CLK0      => ioclk,
+            CLK1      => '0',
+            IOCE      => serdesstrobe,
+            RST       => reset,
+            CLKDIV    => gclk,
+            D4        => mdatain(3),
+            D3        => mdatain(2),
+            D2        => mdatain(1),
+            D1        => mdatain(0),
+--      TQ => ,
+            T1        => '0',
+            T2        => '0',
+            T3        => '0',
+            T4        => '0',
+            TRAIN     => '0',
+            TCE       => '1',
+            SHIFTIN1  => cascade_di,    -- Cascade input D from Master
+            SHIFTIN2  => cascade_ti,    -- Cascade input T from Master
+            SHIFTIN3  => '1',           -- Dummy input in Slave
+            SHIFTIN4  => '1',           -- Dummy input in Slave
+--      SHIFTOUT1 => ,                  -- Dummy output in Slave
+--      SHIFTOUT2 => ,                  -- Dummy output in Slave
+            SHIFTOUT3 => cascade_do,    -- Cascade output D data to Master
+            SHIFTOUT4 => cascade_to);   -- Cascade output T data to Master
 
 end beh;
diff --git a/spartan6/hp_lcd_driver/tmds_encoder.vhdl b/spartan6/hp_lcd_driver/tmds_encoder.vhdl
index 0a83498..40f8dd4 100644
--- a/spartan6/hp_lcd_driver/tmds_encoder.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_encoder.vhdl
@@ -4,26 +4,26 @@ use ieee.numeric_std.all;
 
 entity tmds_encoder is
     port (
-        clk  : in  std_logic;
-	sys_rst_n : in std_logic;
-        blank   : in  std_logic;
-        ctrl : in  std_logic_vector(1 downto 0);
-        din  : in  std_logic_vector(7 downto 0);
-        dout : out std_logic_vector(9 downto 0)
-    );
+        clk       : in  std_logic;
+        sys_rst_n : in  std_logic;
+        blank     : in  std_logic;
+        ctrl      : in  std_logic_vector(1 downto 0);
+        din       : in  std_logic_vector(7 downto 0);
+        dout      : out std_logic_vector(9 downto 0)
+        );
 end tmds_encoder;
 
 architecture beh of tmds_encoder is
     signal n_ones_din : integer range 0 to 8;
 
     signal xored, xnored : std_logic_vector(8 downto 0);
-    signal q_m : std_logic_vector(8 downto 0);
+    signal q_m           : std_logic_vector(8 downto 0);
 
     -- a positive value represents the excess number of 1's that have been transmitted
     -- a negative value represents the excess number of 0's that have been transmitted
     signal disparity : signed(3 downto 0) := to_signed(0, 4);
     -- difference between 1's and 0's (/2 since the last bit is never used)
-    signal diff : signed(3 downto 0) := to_signed(0, 4);
+    signal diff      : signed(3 downto 0) := to_signed(0, 4);
 
 begin
 
@@ -42,7 +42,7 @@ begin
 
     -- create xor encodings
     xored(0) <= din(0);
-    encode_xor: for i in 1 to 7 generate
+    encode_xor : for i in 1 to 7 generate
     begin
         xored(i) <= din(i) xor xored(i - 1);
     end generate;
@@ -50,7 +50,7 @@ begin
 
     -- create xnor encodings
     xnored(0) <= din(0);
-    encode_xnor: for i in 1 to 7 generate
+    encode_xnor : for i in 1 to 7 generate
     begin
         xnored(i) <= din(i) xnor xnored(i - 1);
     end generate;
@@ -83,19 +83,19 @@ begin
                     when others => dout <= "1010101011";
                 end case;
                 disparity <= (others => '0');
-             else
+            else
                 if disparity = 0 or diff = 0 then
                     -- xnored data
                     if q_m(8) = '0' then
-                        dout <= "10" & not q_m(7 downto 0);
+                        dout      <= "10" & not q_m(7 downto 0);
                         disparity <= disparity - diff;
                     -- xored data
                     else
-                        dout <= "01" & q_m(7 downto 0);
+                        dout      <= "01" & q_m(7 downto 0);
                         disparity <= disparity + diff;
                     end if;
                 elsif (diff(diff'left) = '0' and disparity(disparity'left) = '0') or
-                      (diff(diff'left) = '1' and disparity(disparity'left) = '1') then
+                    (diff(diff'left) = '1' and disparity(disparity'left) = '1') then
                     dout <= '1' & q_m(8) & not q_m(7 downto 0);
                     if q_m(8) = '1' then
                         disparity <= disparity + 1 - diff;
@@ -110,7 +110,7 @@ begin
                         disparity <= disparity - 1 + diff;
                     end if;
                 end if;
-             end if;
+            end if;
         end if;
     end process;
 end beh;
diff --git a/spartan6/hp_lcd_driver/tmds_output.vhdl b/spartan6/hp_lcd_driver/tmds_output.vhdl
index 3b29a4c..8f413b8 100644
--- a/spartan6/hp_lcd_driver/tmds_output.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output.vhdl
@@ -7,143 +7,144 @@ use UNISIM.vcomponents.all;
 
 
 entity tmds_output is
-	port (
-	sys_rst_n : in std_logic;
-	 pclk_locked: in std_logic;
-	 pclk: in std_logic;
-	 pclk_x2: in std_logic;
-	 pclk_x10: in std_logic;
-	 serdesstrobe: in std_logic;
-	 r_in: in std_logic_vector(7 downto 0);
-	 g_in: in std_logic_vector(7 downto 0);
-	 b_in: in std_logic_vector(7 downto 0);
-	 hsync: in std_logic;
-	 vsync: in std_logic;
-	blank:  in std_logic;
-	tmds_c_out_p: out std_logic;
-	tmds_c_out_n: out std_logic;
-	tmds_r_out_p: out std_logic;
-	tmds_r_out_n: out std_logic;
-	tmds_g_out_p: out std_logic;
-	tmds_g_out_n: out std_logic;
-	tmds_b_out_p: out std_logic;
-	tmds_b_out_n: out std_logic
-);
+    port (
+        sys_rst_n    : in  std_logic;
+        pclk_locked  : in  std_logic;
+        pclk         : in  std_logic;
+        pclk_x2      : in  std_logic;
+        pclk_x10     : in  std_logic;
+        serdesstrobe : in  std_logic;
+        r_in         : in  std_logic_vector(7 downto 0);
+        g_in         : in  std_logic_vector(7 downto 0);
+        b_in         : in  std_logic_vector(7 downto 0);
+        hsync        : in  std_logic;
+        vsync        : in  std_logic;
+        blank        : in  std_logic;
+        tmds_c_out_p : out std_logic;
+        tmds_c_out_n : out std_logic;
+        tmds_r_out_p : out std_logic;
+        tmds_r_out_n : out std_logic;
+        tmds_g_out_p : out std_logic;
+        tmds_g_out_n : out std_logic;
+        tmds_b_out_p : out std_logic;
+        tmds_b_out_n : out std_logic
+        );
 end tmds_output;
 
 
 architecture beh of tmds_output is
 
-signal ctrl: std_logic_vector(1 downto 0);
-signal r_p10:std_logic_vector(9 downto 0);
-signal g_p10:std_logic_vector(9 downto 0);
-signal b_p10:std_logic_vector(9 downto 0);
-
-signal phy_reset: std_logic;
-signal bufpll_lock:std_logic;
-signal upper:std_logic;
-begin 
-
-
-   ctrl <= vsync & hsync;
-
-
-
-
-    enc_r: entity work.tmds_encoder 
-	port map (
-		sys_rst_n => sys_rst_n,
-		clk => pclk,
-		ctrl => ctrl,
-		blank => blank,
-		din => r_in,
-		dout => r_p10
-		);
-
-
-    enc_g: entity work.tmds_encoder 
-	port map (
-		sys_rst_n => sys_rst_n,
-		clk => pclk,
-		ctrl => "11",
-		blank => blank,
-		din => g_in,
-		dout => g_p10
-		);
-
-
-
-    enc_b: entity work.tmds_encoder 
-	port map (
-		sys_rst_n => sys_rst_n,
-		clk => pclk,
-		ctrl => "11",
-		blank => blank,
-		din => b_in,
-		dout => b_p10
-		);
-
-
-   phy_reset <= not sys_rst_n or not bufpll_lock;
-
-	process (pclk_x2) begin
-	if phy_reset='1' then
-		upper<='1';
-	elsif rising_edge(pclk_x2) then
-		upper<= not upper;
-	end if ;
-	end process;
-
-
-phy_c : entity work.tmds_phy 
-	port map (
-	reset => phy_reset,
-	pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe,
-	ioclk => pclk_x10,
-	upper => upper,
-	din => "1111100000",
-	tmds_out_p => tmds_c_out_p,
-	tmds_out_n => tmds_c_out_n
-);
-
-phy_r : entity work.tmds_phy 
-	port map (
-	reset => phy_reset,
-	 pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe,
-	ioclk=>pclk_x10,
-	upper=>upper,
-	 din => r_p10,
-	tmds_out_p => tmds_r_out_p,
-	tmds_out_n => tmds_r_out_n
-);
-
-
-phy_g : entity work.tmds_phy 
-	port map (
-	reset => phy_reset,
-	 pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe,
-	ioclk=>pclk_x10,
-	upper=>upper,
-	 din => g_p10,
-	tmds_out_p => tmds_g_out_p,
-	tmds_out_n => tmds_g_out_n
-);
-
-
-phy_b : entity work.tmds_phy 
-	port map (
-	reset => phy_reset,
-	 pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe,
-	ioclk=>pclk_x10,
-	upper=>upper,
-	 din => b_p10,
-	tmds_out_p => tmds_b_out_p,
-	tmds_out_n => tmds_b_out_n
-);
+    signal ctrl  : std_logic_vector(1 downto 0);
+    signal r_p10 : std_logic_vector(9 downto 0);
+    signal g_p10 : std_logic_vector(9 downto 0);
+    signal b_p10 : std_logic_vector(9 downto 0);
+
+    signal phy_reset   : std_logic;
+    signal bufpll_lock : std_logic;
+    signal upper       : std_logic;
+begin
+
+
+    ctrl <= vsync & hsync;
+
+
+
+
+    enc_r : entity work.tmds_encoder
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => pclk,
+            ctrl      => ctrl,
+            blank     => blank,
+            din       => r_in,
+            dout      => r_p10
+            );
+
+
+    enc_g : entity work.tmds_encoder
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => pclk,
+            ctrl      => "11",
+            blank     => blank,
+            din       => g_in,
+            dout      => g_p10
+            );
+
+
+
+    enc_b : entity work.tmds_encoder
+        port map (
+            sys_rst_n => sys_rst_n,
+            clk       => pclk,
+            ctrl      => "11",
+            blank     => blank,
+            din       => b_in,
+            dout      => b_p10
+            );
+
+
+    phy_reset <= not sys_rst_n or not bufpll_lock;
+
+    process (pclk_x2)
+    begin
+        if phy_reset = '1' then
+            upper <= '1';
+        elsif rising_edge(pclk_x2) then
+            upper <= not upper;
+        end if;
+    end process;
+
+
+    phy_c : entity work.tmds_phy
+        port map (
+            reset        => phy_reset,
+            pclk_x2      => pclk_x2,
+            serdesstrobe => serdesstrobe,
+            ioclk        => pclk_x10,
+            upper        => upper,
+            din          => "1111100000",
+            tmds_out_p   => tmds_c_out_p,
+            tmds_out_n   => tmds_c_out_n
+            );
+
+    phy_r : entity work.tmds_phy
+        port map (
+            reset        => phy_reset,
+            pclk_x2      => pclk_x2,
+            serdesstrobe => serdesstrobe,
+            ioclk        => pclk_x10,
+            upper        => upper,
+            din          => r_p10,
+            tmds_out_p   => tmds_r_out_p,
+            tmds_out_n   => tmds_r_out_n
+            );
+
+
+    phy_g : entity work.tmds_phy
+        port map (
+            reset        => phy_reset,
+            pclk_x2      => pclk_x2,
+            serdesstrobe => serdesstrobe,
+            ioclk        => pclk_x10,
+            upper        => upper,
+            din          => g_p10,
+            tmds_out_p   => tmds_g_out_p,
+            tmds_out_n   => tmds_g_out_n
+            );
+
+
+    phy_b : entity work.tmds_phy
+        port map (
+            reset        => phy_reset,
+            pclk_x2      => pclk_x2,
+            serdesstrobe => serdesstrobe,
+            ioclk        => pclk_x10,
+            upper        => upper,
+            din          => b_p10,
+            tmds_out_p   => tmds_b_out_p,
+            tmds_out_n   => tmds_b_out_n
+            );
 
 
 
diff --git a/spartan6/hp_lcd_driver/tmds_phy.vhdl b/spartan6/hp_lcd_driver/tmds_phy.vhdl
index 84c37f9..ece67e6 100644
--- a/spartan6/hp_lcd_driver/tmds_phy.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_phy.vhdl
@@ -6,61 +6,62 @@ library UNISIM;
 use UNISIM.vcomponents.all;
 
 entity tmds_phy is
-	port (
-	reset : in std_logic;
-	 pclk_x2: in std_logic;
-	 ioclk: in std_logic;
-	    serdesstrobe: in std_logic;
-        din: in std_logic_vector(9 downto 0);
-	upper: in std_logic;
-	tmds_out_p: out std_logic;
-	tmds_out_n: out std_logic
-);
+    port (
+        reset        : in  std_logic;
+        pclk_x2      : in  std_logic;
+        ioclk        : in  std_logic;
+        serdesstrobe : in  std_logic;
+        din          : in  std_logic_vector(9 downto 0);
+        upper        : in  std_logic;
+        tmds_out_p   : out std_logic;
+        tmds_out_n   : out std_logic
+        );
 end tmds_phy;
 
 
 architecture beh of tmds_phy is
 
-signal din_s:std_logic_vector(9 downto 0);
-signal p5_n:std_logic_vector(4 downto 0);
-signal p5:std_logic_vector(4 downto 0);
-signal s:std_logic;
+    signal din_s : std_logic_vector(9 downto 0);
+    signal p5_n  : std_logic_vector(4 downto 0);
+    signal p5    : std_logic_vector(4 downto 0);
+    signal s     : std_logic;
 
 
 
-begin 
+begin
 
-	process (pclk_x2) begin
-	if rising_edge(pclk_x2) then
-	   if upper='1'  then
-		din_s <= din;
-		p5 <= din_s(9 downto 5);
-		p5_n <= din_s(4 downto 0);
-	   else 
-		p5<=p5_n;
-	 end if;
-	end if;
-	end process;
+    process (pclk_x2)
+    begin
+        if rising_edge(pclk_x2) then
+            if upper = '1' then
+                din_s <= din;
+                p5    <= din_s(9 downto 5);
+                p5_n  <= din_s(4 downto 0);
+            else
+                p5 <= p5_n;
+            end if;
+        end if;
+    end process;
 
 
     serdes : entity work.serdes_n_to_1
-        generic map(SF=>5)
+        generic map(SF => 5)
         port map (
-	    ioclk => ioclk,
-	    serdesstrobe => serdesstrobe,
-		reset => reset,
-		gclk => pclk_x2,
-		datain => p5,
-		iob_data_out =>s
-	);
+            ioclk        => ioclk,
+            serdesstrobe => serdesstrobe,
+            reset        => reset,
+            gclk         => pclk_x2,
+            datain       => p5,
+            iob_data_out => s
+            );
+
+    obuf : OBUFDS
+        generic map (IOSTANDARD => "TMDS_33")
+        port map (
+            I  =>s,
+            O  =>tmds_out_p,
+            OB => tmds_out_n
+            );
 
-   obuf : OBUFDS
-	generic map ( IOSTANDARD => "TMDS_33")
-	port map (
-	I=>s,
-	O=>tmds_out_p,
-	OB=>tmds_out_n
-	);
-	
 
 end beh;