meets timing

4 files changed, 74 insertions, 102 deletions

diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
index bef419f..4864b7c 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.ucf
@@ -1,7 +1,7 @@
 #NET "hdmi_r" IOSTANDARD = LVCMOS33;
 #NET "hdmi_b" LOC = P67;
 
-NET "clk_50m_in" IOSTANDARD = LVCMOS33;
+NET "clk_50m" IOSTANDARD = LVCMOS33;
 NET "sys_rst_n" IOSTANDARD = LVCMOS33;
 NET "video(0)" IOSTANDARD = LVCMOS33;
 NET "video(1)" IOSTANDARD = LVCMOS33;
@@ -13,14 +13,9 @@ NET "g_out" IOSTANDARD = LVCMOS33;
 NET "hsync_out" IOSTANDARD = LVCMOS33;
 NET "vsync_out" IOSTANDARD = LVCMOS33;
 
-#NET "hdmi_c_p" LOC = P142;
-#NET "hdmi_c_n" LOC = P141;
-#NET "hdmi_r_p" LOC = P140;
-#NET "hdmi_r_n" LOC = P139;
-#NET "hdmi_g_p" LOC = P138;
-#NET "hdmi_g_n" LOC = P137;
-#NET "hdmi_b_p" LOC = P44;
-#NET "hdmi_b_n" LOC = P43;
+
+INST "pll"   LOC = "PLL_ADV_X0Y1";
+INST "ioclk_buf"     LOC = "BUFPLL_X1Y0";
 
 
 
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index a6de250..85e04e3 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -36,7 +36,7 @@ use UNISIM.vcomponents.all;
 entity hp_lcd_driver is
     generic (video_width : natural := 2;
              addr_width  : natural := 18);
-    port (clk_50m_in : in  std_logic;
+    port (clk_50m : in  std_logic;
           sys_rst_n  : in  std_logic;
           video      : in  std_logic_vector(video_width-1 downto 0);
           hsync_in   : in  std_logic;
@@ -74,52 +74,75 @@ architecture Behavioral of hp_lcd_driver is
     signal i_clk   : std_logic;
 
     signal o_clk_locked   : std_logic;
---    signal o_clk_ub   : std_logic;
     signal o_clk   : std_logic;
---    signal o_clk_x2_ub   : std_logic;
     signal o_clk_x2   : std_logic;
     signal o_clk_x10   : std_logic;
+    signal serdesstrobe : std_logic;
 
-    signal clk_50m : std_logic;
+    signal clkfbout:std_logic;
+    signal clk_200m:std_logic;
+    signal clk_80m:std_logic;
+    signal clk_40m:std_logic;
+    signal clk_20m:std_logic;
+    signal pll_locked:std_logic;
+    signal pll_locked_n:std_logic;
 
     signal sys_rst : std_logic;
 
+
 begin
 
-    sys_rst <= not sys_rst_n;
 
-    clk_buf : BUFG
-        port map (
-            I => clk_50m_in,
-            O => clk_50m
-            );
 
 
-    ipll : entity work.pll_50_80
-        port map (
-            reset      => sys_rst,
-            clk_50_in  => clk_50m,
-            clk_80_out => i_clk
-            );
+pll: PLL_BASE generic map (
+	CLKIN_PERIOD=>20.0,
+	CLKFBOUT_MULT => 8,
+	CLKOUT0_DIVIDE => 2,
+	CLKOUT1_DIVIDE => 5,
+	CLKOUT2_DIVIDE => 10,
+	CLKOUT3_DIVIDE => 20,
+	COMPENSATION => "INTERNAL")
+	port map (
+	CLKFBOUT => clkfbout,
+	CLKOUT0 => clk_200m,
+	CLKOUT1 => clk_80m,
+	CLKOUT2 => clk_40m,
+	CLKOUT3 => clk_20m,
+	LOCKED => pll_locked,
+	CLKFBIN => clkfbout,
+	CLKIN => clk_50m,
+	RST => pll_locked_n);
+
+pll_locked_n <= not pll_locked;
+
+
+
+
+ioclk_buf: BUFPLL generic map ( DIVIDE=>5)
+	port map (
+		PLLIN=>clk_200m,
+		GCLK=>o_clk_x2,
+		LOCKED => pll_locked,
+		IOCLK => o_clk_x10,
+		SERDESSTROBE => serdesstrobe,
+		LOCK => o_clk_locked);
+
+o_clk_buf: BUFG port map (
+	I=>clk_20m,
+	O=>o_clk);
+
+	
+o_clk_x2_buf: BUFG port map (
+	I=>clk_40m,
+	O=>o_clk_x2);
+
+	
+i_clk_buf: BUFG port map (
+	I=>clk_80m,
+	O=>i_clk);
 
-    opll : entity work.pll_50_p10_p2_p
-        port map (
-            reset          => sys_rst,
-            clk_50_in      => clk_50m,
-            pclk_x10_out => o_clk_x10,
-            pclk_x2_out => o_clk_x2,
-	    pclk_out	=> o_clk,
-	    LOCKED	=> o_clk_locked
-            );
 
---    o_clk_x2_buf: BUFG port map (
---		I=>o_clk_x2_ub,
---		O=>o_clk_x2
---	);
---    o_clk_buf: BUFG port map (
---		I=>o_clk_ub,
---		O=>o_clk
---	);
 
     input0 : entity work.input_stage
         generic map(
@@ -144,7 +167,8 @@ begin
             addr_out  => wr_addr,
             wren_out  => wr_en(0));
 
-    vram0 : entity work.vram
+
+    VRAM0 : entity work.vram
         port map (
             clka  => i_clk,
             wea   => wr_en,
@@ -187,6 +211,7 @@ begin
             clk       => o_clk,
 	    clk_x2	=> o_clk_x2,		
 	    clk_x10	=> o_clk_x10,		
+	    serdesstrobe => serdesstrobe,
             sys_rst_n => sys_rst_n,
             vsync_in  => vsync_in,
             r_in    => r,
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index 8c33685..8a8ab44 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -28,6 +28,7 @@ entity output_stage is
             clk       : in std_logic;
             clk_x2       : in std_logic;
             clk_x10       : in std_logic;
+            serdesstrobe       : in std_logic;
             sys_rst_n : in std_logic;
 
             vsync_in : in std_logic;
@@ -145,6 +146,7 @@ output_tmds: entity work.tmds_output
             pclk       => clk,
             pclk_x2       => clk_x2,
             pclk_x10       => clk_x10,
+	    serdesstrobe => serdesstrobe,
 
 		r_in => r_in,
 		g_in => g_in,
diff --git a/spartan6/hp_lcd_driver/tmds_output.vhdl b/spartan6/hp_lcd_driver/tmds_output.vhdl
index 096b5b7..3b29a4c 100644
--- a/spartan6/hp_lcd_driver/tmds_output.vhdl
+++ b/spartan6/hp_lcd_driver/tmds_output.vhdl
@@ -13,6 +13,7 @@ entity tmds_output is
 	 pclk: in std_logic;
 	 pclk_x2: in std_logic;
 	 pclk_x10: in std_logic;
+	 serdesstrobe: in std_logic;
 	 r_in: in std_logic_vector(7 downto 0);
 	 g_in: in std_logic_vector(7 downto 0);
 	 b_in: in std_logic_vector(7 downto 0);
@@ -41,9 +42,6 @@ signal b_p10:std_logic_vector(9 downto 0);
 signal phy_reset: std_logic;
 signal bufpll_lock:std_logic;
 signal upper:std_logic;
-signal ioclk: std_logic_vector(3 downto 0);
-signal serdesstrobe:std_logic_vector(3 downto 0);
-
 begin 
 
 
@@ -86,54 +84,6 @@ begin
 		);
 
 
-ioclk_buf_0:   BUFPLL 
-	generic map ( DIVIDE => 5)
-	port map ( 
-		PLLIN => pclk_x10,
-		GCLK => pclk_x2,
-		LOCKED => pclk_locked,
-		IOCLK => ioclk(0),
-		SERDESSTROBE => serdesstrobe(0)
-	);
-		
-
-
-ioclk_buf_1:   BUFPLL 
-	generic map ( DIVIDE => 5)
-	port map ( 
-		PLLIN => pclk_x10,
-		GCLK => pclk_x2,
-		LOCKED => pclk_locked,
-		IOCLK => ioclk(1),
-		SERDESSTROBE => serdesstrobe(1)
-	);
-		
-
-
-ioclk_buf_2:   BUFPLL 
-	generic map ( DIVIDE => 5)
-	port map ( 
-		PLLIN => pclk_x10,
-		GCLK => pclk_x2,
-		LOCKED => pclk_locked,
-		IOCLK => ioclk(2),
-		SERDESSTROBE => serdesstrobe(2)
-	);
-		
-
-
-ioclk_buf_3:   BUFPLL 
-	generic map ( DIVIDE => 5)
-	port map ( 
-		PLLIN => pclk_x10,
-		GCLK => pclk_x2,
-		LOCKED => pclk_locked,
-		IOCLK => ioclk(3),
-		SERDESSTROBE => serdesstrobe(3)
-	);
-		
-
-
    phy_reset <= not sys_rst_n or not bufpll_lock;
 
 	process (pclk_x2) begin
@@ -149,8 +99,8 @@ phy_c : entity work.tmds_phy
 	port map (
 	reset => phy_reset,
 	pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe(0),
-	ioclk => ioclk(0),
+	serdesstrobe => serdesstrobe,
+	ioclk => pclk_x10,
 	upper => upper,
 	din => "1111100000",
 	tmds_out_p => tmds_c_out_p,
@@ -161,8 +111,8 @@ phy_r : entity work.tmds_phy
 	port map (
 	reset => phy_reset,
 	 pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe(1),
-	ioclk=>ioclk(1),
+	serdesstrobe => serdesstrobe,
+	ioclk=>pclk_x10,
 	upper=>upper,
 	 din => r_p10,
 	tmds_out_p => tmds_r_out_p,
@@ -174,8 +124,8 @@ phy_g : entity work.tmds_phy
 	port map (
 	reset => phy_reset,
 	 pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe(2),
-	ioclk=>ioclk(2),
+	serdesstrobe => serdesstrobe,
+	ioclk=>pclk_x10,
 	upper=>upper,
 	 din => g_p10,
 	tmds_out_p => tmds_g_out_p,
@@ -187,8 +137,8 @@ phy_b : entity work.tmds_phy
 	port map (
 	reset => phy_reset,
 	 pclk_x2 => pclk_x2,
-	serdesstrobe => serdesstrobe(3),
-	ioclk=>ioclk(3),
+	serdesstrobe => serdesstrobe,
+	ioclk=>pclk_x10,
 	upper=>upper,
 	 din => b_p10,
 	tmds_out_p => tmds_b_out_p,