working

3 files changed, 55 insertions, 20 deletions

diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
index 51d5c38..d21cd2b 100644
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -55,6 +55,12 @@ architecture Behavioral of hp_lcd_driver is
 begin
 
 
+-- clocking:
+-- i_clk is 4*20MHz to give us 4 choices of sampling position
+-- o_clk is the output pixel clock
+-- o_clk_x2 is used by the spartan serdes
+-- o_clk_phy is used the the hdmi phy (cylone4 it's o_clk x5, spartan 6 it's o_clk x 10)
+
     clkgen : entity work.clkgen
         port map (
             sys_rst_n => sys_rst_n,
@@ -111,27 +117,27 @@ begin
     g <= x"ff" when rd_data(0) = '1' else
          x"ff" when rd_data(1) = '1' else
          x"00";
-    --b <= x"ff" when rd_data(1) = '1' else
-    --     x"00";
-
-	b<=x"ff";
+    b <= x"ff" when rd_data(1) = '1' else
+         x"00";
 
 
 
     output0 : entity work.output_stage
 
--- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
+-- didn't work for me from this thing, only from mac, works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
+--  Modeline "384x592_80.00"  25.40  384 408 448 512  592 593 596 620  -HSync +Vsync
+
         generic map (
             target       => target,
             addr_width   => addr_width,
             h_active     => 384,
             h_sync_start => 400,
             h_sync_end   => 440,
-            h_total      => 600,
+            h_total      => 620,
             v_active     => 592,
             v_sync_start => 593,
             v_sync_end   => 596,
-            v_total      => 614,
+            v_total      => 613,
             h_stride     => 1,
             v_stride     => 384
             )
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
index f490c8b..d34bc06 100644
--- a/spartan6/hp_lcd_driver/output_formatter.vhdl
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -25,7 +25,9 @@ entity output_formatter is
         addr_out  : out std_logic_vector(addr_width -1 downto 0);
         blank_out : out std_logic;
         vsync_out : out std_logic;
-        hsync_out : out std_logic
+        hsync_out : out std_logic;
+        h_grid : out std_logic;
+        v_grid : out std_logic
         );
 end output_formatter;
 
@@ -117,6 +119,12 @@ begin
         end if;
     end process;
 
+    h_grid <='1' when (h mod 8)=0
+		else '0';
+
+    v_grid <='1' when (v mod 8)=0
+		else '0';
+
 
     addr_out  <= addr;
     blank_out <= blank;
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
index 19e9d35..41b1760 100644
--- a/spartan6/hp_lcd_driver/output_stage.vhdl
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -67,6 +67,12 @@ architecture beh of output_stage is
 
     signal addr : std_logic_vector(addr_width - 1 downto 0);
 
+    signal r : std_logic_vector(7 downto 0);
+    signal g : std_logic_vector(7 downto 0);
+    signal b : std_logic_vector(7 downto 0);
+
+signal            h_grid    : std_logic;
+signal            v_grid  : std_logic;
 
     signal r_p10 : std_logic_vector(9 downto 0);
     signal g_p10 : std_logic_vector(9 downto 0);
@@ -105,7 +111,8 @@ begin
             v_sync_end   => v_sync_end,
             v_total      => v_total,
             h_stride     => h_stride,
-            v_stride     => v_stride)
+            v_stride     => v_stride
+	)
         port map (
             sys_rst_n => sys_rst_n,
             clk       => clk,
@@ -113,13 +120,27 @@ begin
             addr_out  => addr,
             blank_out => blank,
             vsync_out => vsync,
-            hsync_out => hsync
+            hsync_out => hsync,
+	    h_grid	 => h_grid,
+	    v_grid	 => v_grid
             );
 
 
     addr_out <= addr;
 
 
+    b<=b_in;
+
+    r<=x"00" when h_grid='0'
+	    else x"ff";
+
+    g<=x"00" when v_grid='0'
+	    else x"ff";
+
+
+
+
+
     analog : entity work.output_analog
         port map(
             sys_rst_n => sys_rst_n,
@@ -129,9 +150,9 @@ begin
             hsync_in => hsync,
             vsync_in => vsync,
             blank_in => blank,
-            r_in     => g_in(7),
-            g_in     => g_in(6),
-            b_in     => b_in(7),
+            r_in     => g(7),
+            g_in     => r(7),
+            b_in     => b(7),
 
             r_out     => r_out,
             g_out     => g_out,
@@ -145,9 +166,9 @@ begin
         sys_rst_n => sys_rst_n,
         pclk      => clk,
 
-        r_in  => r_in,
-        g_in  => g_in,
-        b_in  => b_in,
+        r_in  => r,
+        g_in  => g,
+        b_in  => b,
         hsync => hsync,
         vsync => vsync,
         blank => blank,
@@ -175,12 +196,12 @@ begin
 
             tmds_c_out_p => hdmi_c_p,
             tmds_c_out_n => hdmi_c_n,
-            tmds_r_out_p => hdmi_b_p,
-            tmds_r_out_n => hdmi_b_n,
+            tmds_r_out_p => hdmi_r_p,
+            tmds_r_out_n => hdmi_r_n,
             tmds_g_out_p => hdmi_g_p,
             tmds_g_out_n => hdmi_g_n,
-            tmds_b_out_p => hdmi_r_p,
-            tmds_b_out_n => hdmi_r_n
+            tmds_b_out_p => hdmi_b_p,
+            tmds_b_out_n => hdmi_b_n
             );