before tidy

14 files changed, 1481 insertions, 109 deletions

diff --git a/spartan6/hp_lcd_driver/Makefile b/spartan6/hp_lcd_driver/Makefile
index d526ede..b3ae3ea 100644
--- a/spartan6/hp_lcd_driver/Makefile
+++ b/spartan6/hp_lcd_driver/Makefile
@@ -3,13 +3,14 @@ include relpath.mk
 PART=xc6slx9-2-tqg144
 TOP=hp_lcd_driver
 BUILD=build
-VSRCS=hp_lcd_driver.vhd
+VSRCS=synchronizer.vhdl debounce.vhdl edge_det.vhdl input_formatter.vhdl input_stage.vhdl output_formatter.vhdl output_analog.vhdl output_stage.vhdl hp_lcd_driver.vhdl
 UCF=hp_lcd_driver.ucf
 UT=hp_lcd_driver.ut
-IPSRCS=vram.xco
-
+IPSRCS= pll_50_80.xco pll_50_91_18.xco vram.xco
 DESIGN_NAME=${TOP}
-ISE_BINDIR=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64
+ISE_HOME=/software/apps/xilinx/ISE/14.7/ISE_DS/ISE
+ISE_BINDIR_32=${ISE_HOME}/bin/lin
+ISE_BINDIR_64=${ISE_HOME}/bin/lin64
 INTSTYLE=
 
 XST_FLAGS=${INTSTYLE}
@@ -54,7 +55,7 @@ ${PRJ}: ${VSRCS} ${GEN_VSRCS}
 	done ;
 
 ${NGC}:${XST}
-	(cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD}))
+	(cd ${BUILD} && mkdir -p ${XST_DIR} ${XST_TMPDIR} && ${ISE_BINDIR_64}/xst ${XST_FLAGS} -ifn $(call relpath,$<,${BUILD}) -ofn $(call relpath,${SYR},${BUILD}))
 
 ${XST}: ${PRJ} ${DESIGN_NAME}.xst_template
 	rm -f  $@
@@ -67,19 +68,19 @@ ${XST}: ${PRJ} ${DESIGN_NAME}.xst_template
 	echo "-top ${TOP}" >> $@
 
 ${NGD}:${NGC} ${UCF}
-	(cd ${BUILD} && ${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD}))
+	(cd ${BUILD} && ${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -uc $(call relpath,${UCF},${BUILD}) $(call relpath,${NGC},${BUILD}) $(call relpath,$@,${BUILD}))
 
 ${MAP_NCD} ${PCF}:${NGD}
-	(cd ${BUILD} && ${ISE_BINDIR}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD})  $(call relpath,${PCF},${BUILD}))
+	(cd ${BUILD} && ${ISE_BINDIR_64}/map $(MAP_FLAGS) -o $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NGD},${BUILD})  $(call relpath,${PCF},${BUILD}))
 
 ${NCD}: ${MAP_NCD} ${PCF}
-	(cd ${BUILD} && ${ISE_BINDIR}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD}))
+	(cd ${BUILD} && ${ISE_BINDIR_64}/par $(PAR_FLAGS) $(call relpath,${MAP_NCD},${BUILD}) $(call relpath,${NCD},${BUILD}) $(call relpath,${PCF},${BUILD}))
 
 ${TWR} ${TWX}: ${NCD} ${PCF}
-	(cd ${BUILD} && ${ISE_BINDIR}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD}))
+	(cd ${BUILD} && ${ISE_BINDIR_64}/trce ${TRCE_FLAGS} -xml $(call relpath,${TWX},${BUILD}) $(call relpath,${NCD},${BUILD}) -o $(call relpath,${TWR},${BUILD}) $(call relpath,${PCF},${BUILD}))
 
 ${BIT}:${NCD} ${UT}
-	(cd ${BUILD} && ${ISE_BINDIR}/bitgen ${BITGEN_FLAGS} -f  $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD}))
+	(cd ${BUILD} && ${ISE_BINDIR_64}/bitgen ${BITGEN_FLAGS} -f  $(call relpath,${UT},${BUILD}) $(call relpath,${NCD},${BUILD}))
 
 ${SVF}:${BIT}
 	( cd ${BUILD} && \
@@ -88,12 +89,17 @@ ${SVF}:${BIT}
 	addDevice -p 1 -file \"$(call relpath,${BIT},${BUILD})\" \n\
 	program -p 1 \n\
 	quit \n" > impact.run &&\
-	${ISE_BINDIR}/impact -batch impact.run)
+	${ISE_BINDIR_64}/impact -batch impact.run)
 
 
 ${BUILD}/%.vhd:%.xco
 	mkdir -p ${BUILD}
-	(cd ${BUILD} && touch empty.prj  && ${ISE_BINDIR}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj)
+	(cd ${BUILD} && touch empty.prj  && ${ISE_BINDIR_32}/coregen -b $(call relpath,$<,${BUILD}) -p empty.prj)
+
+
+tidy:
+	git diff --exit-code -s source	
+	for i in ${VSRCS}; do /bin/cp -f $$i $$i.orig && scripts/vhdl-pretty < $$i.orig > $$i; done
 
 
 #
@@ -191,33 +197,33 @@ ${BUILD}/%.vhd:%.xco
 #		"-p $(PART)" \
 #		"-top $(TOP_NAME)" \
 #			> $(PROJNAV_DIR)/tmp.xst
-#	${ISE_BINDIR}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr
+#	${ISE_BINDIR_64}/xst $(XST_FLAGS) -ifn $(PROJNAV_DIR)/tmp.xst -ofn $*.syr
 #
 ## Take the output of the synthesizer and create the NGD file.  This rule
 ## will also be triggered if constraints file is changed.
 #%.ngd: %.ngc %.ucf
-#	${ISE_BINDIR}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd
+#	${ISE_BINDIR_64}/ngdbuild $(NGDBUILD_FLAGS) -p $(PART) $*.ngc $*.ngd
 #
 ## Map the NGD file and physical-constraints to the FPGA to create the mapped NCD file.
 #%_map.ncd %.pcf: %.ngd
-#	${ISE_BINDIR}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf
+#	${ISE_BINDIR_64}/map $(MAP_FLAGS) -p $(PART) -o $*_map.ncd $*.ngd $*.pcf
 #
 ## Place & route the mapped NCD file to create the final NCD file.
 #%.ncd: %_map.ncd %.pcf
-#	${ISE_BINDIR}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf
+#	${ISE_BINDIR_64}/par $(PAR_FLAGS) $*_map.ncd $*.ncd $*.pcf
 #
 ## Take the final NCD file and create an FPGA bitstream file.  This rule will also be
 ## triggered if the bit generation options file is changed.
 #%.bit: %.ncd $(BITGEN_OPTIONS_FILE)
-#	${ISE_BINDIR}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd
+#	${ISE_BINDIR_64}/bitgen $(BITGEN_FLAGS) -f $(BITGEN_OPTIONS_FILE) $*.ncd
 #
 ## Convert a bitstream file into an MCS hex file that can be stored into Flash memory.
 #%.mcs: %.bit
-#	${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs
+#	${ISE_BINDIR_64}/promgen $(PROMGEN_FLAGS) $*.bit -p mcs
 #
 ## Convert a bitstream file into an EXO hex file that can be stored into Flash memory.
 #%.exo: %.bit
-#	${ISE_BINDIR}/promgen $(PROMGEN_FLAGS) $*.bit -p exo
+#	${ISE_BINDIR_64}/promgen $(PROMGEN_FLAGS) $*.bit -p exo
 #
 ## Use .config suffix to trigger creation of a bit/svf file
 ## depending upon whether an FPGA is the target device.
@@ -225,7 +231,7 @@ ${BUILD}/%.vhd:%.xco
 #
 ## Create the FPGA timing report after place & route.
 #%.twr: %.ncd %.pcf
-#	${ISE_BINDIR}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf
+#	${ISE_BINDIR_64}/trce $(TRCE_FLAGS) $*.ncd -o $*.twr $*.pcf
 #
 ## Use .timing suffix to trigger timing report creation.
 #%.timing: %.twr ;
@@ -258,20 +264,20 @@ ${BUILD}/%.vhd:%.xco
 #	assignFile -p 1 -file $(DESIGN_NAME).bit \n\
 #	program -p 1 \n\
 #	quit \n" > impact.run
-#	${ISE_BINDIR}/impact -batch impact.run
+#	${ISE_BINDIR_64}/impact -batch impact.run
 #
 ##Simulation using ModelSIM
 #setlib:
-#	${ISE_BINDIR}/vlib work
+#	${ISE_BINDIR_64}/vlib work
 #
 #vsim-compile: setlib $(SIM_FILES) $(HDL_FILES)
-#	${ISE_BINDIR}/vcom $(HDL_FILES)  $(SIM_FILES)
+#	${ISE_BINDIR_64}/vcom $(HDL_FILES)  $(SIM_FILES)
 #
 #vsim: vsim-compile
-#	${ISE_BINDIR}/vsim  $(TESTBENCH_NAME)
+#	${ISE_BINDIR_64}/vsim  $(TESTBENCH_NAME)
 #
 #vsim-run: vsim-compile
-#	${ISE_BINDIR}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME)
+#	${ISE_BINDIR_64}/vsim -c -do "run -all; quit" $(TESTBENCH_NAME)
 #
 ##
 ## Default targets for FPGA compilations.
diff --git a/spartan6/hp_lcd_driver/debounce.vhdl b/spartan6/hp_lcd_driver/debounce.vhdl
new file mode 100644
index 0000000..654a2f3
--- /dev/null
+++ b/spartan6/hp_lcd_driver/debounce.vhdl
@@ -0,0 +1,32 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity debounce is
+    generic (stages : natural := 1);
+    port (clk : in  std_logic;
+          i   : in  std_logic;
+          o   : out std_logic);
+end debounce;
+
+architecture Behavioral of debounce is
+    signal flipflops : std_logic_vector(stages-1 downto 0) := (others => '0');
+    constant zero    : std_logic_vector(stages-1 downto 0) := (others => '0');
+    constant one     : std_logic_vector(stages-1 downto 0) := (others => '1');
+    signal output    : std_logic                           := '0';
+begin
+
+    o <= output;
+
+    process (clk,flipflops,i)
+    begin
+        if rising_edge(clk) then
+            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+            if flipflops = one and i = '1' then
+                output <= '1';
+            elsif flipflops = zero and i = '0' then
+                output <= '0';
+            end if;
+        end if;
+    end process;
+
+end architecture;
diff --git a/spartan6/hp_lcd_driver/edge_det.vhdl b/spartan6/hp_lcd_driver/edge_det.vhdl
new file mode 100644
index 0000000..8cb38eb
--- /dev/null
+++ b/spartan6/hp_lcd_driver/edge_det.vhdl
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity edge_det is
+    port (clk : in  std_logic;
+          sig : in  std_logic;
+          pe  : out std_logic;
+          ne  : out std_logic;
+          e   : out std_logic
+          );
+end edge_det;
+
+architecture Behavioral of edge_det is
+    signal last : std_logic := '0';
+begin
+
+    process(clk,last,sig) 
+    begin
+        if rising_edge(clk) then
+            last <= sig;
+        end if;
+    end process;
+
+    pe <= '1' when sig = '1' and last = '0' else '0';
+    ne <= '1' when sig = '0' and last = '1' else '0';
+
+    e <= sig xor last;
+end Behavioral;
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhd b/spartan6/hp_lcd_driver/hp_lcd_driver.vhd
deleted file mode 100644
index 9b7aac9..0000000
--- a/spartan6/hp_lcd_driver/hp_lcd_driver.vhd
+++ /dev/null
@@ -1,84 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    13:20:32 04/26/2025 
--- Design Name: 
--- Module Name:    hp_lcd_driver - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.NUMERIC_STD.ALL;
-use work.all;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity hp_lcd_driver is
-    Port ( clk_50m : in  STD_LOGIC;
-	   sys_rst_n : in STD_LOGIC;
-           hdmi_clk : out  STD_LOGIC;
-           hdmi_r : out  STD_LOGIC;
-           hdmi_g : out  STD_LOGIC;
-           hdmi_b : out  STD_LOGIC;
-           video : in  STD_LOGIC;
-           bright : in  STD_LOGIC;
-           hsync : in  STD_LOGIC;
-           vsync : in  STD_LOGIC);
-end hp_lcd_driver;
-
-architecture Behavioral of hp_lcd_driver is
-
-signal addr : std_logic_vector(17 downto 0);
-signal dout : std_logic_vector(1 downto 0);
-signal din : std_logic_vector(1 downto 0);
-
-begin
-
-hdmi_clk <= clk_50m;
-hdmi_b<='0';
-
-din <=(video,bright);
-
-vram0: entity work.vram
-	port map (
-	clka => clk_50m,
-	wea => "1",
-	addra => addr,
-	dina => din,
-	clkb => clk_50m,
-	addrb => addr,
-	doutb => dout
-);
-
-hdmi_g <= dout(0);
-hdmi_r <= dout(1);
-
-   process (sys_rst_n,clk_50m)  begin
-                if sys_rst_n = '0' then
-                        addr <=(others =>'0');
-                elsif rising_edge(clk_50m) then
-                   addr <= std_logic_vector(unsigned(addr)+1);
-                end if;
-        end process;
-
-
-
-end Behavioral;
-
diff --git a/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
new file mode 100644
index 0000000..0789102
--- /dev/null
+++ b/spartan6/hp_lcd_driver/hp_lcd_driver.vhdl
@@ -0,0 +1,177 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    13:20:32 04/26/2025 
+-- Design Name: 
+-- Module Name:    hp_lcd_driver - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+use work.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity hp_lcd_driver is
+    generic (video_width     : natural := 2;
+	     addr_width      : natural := 18);
+    port ( clk_50m_in : in  STD_LOGIC;
+	   sys_rst_n : in STD_LOGIC;
+           video : in  std_logic_vector(video_width-1 downto 0);
+           hsync_in : in  STD_LOGIC;
+           vsync_in : in  STD_LOGIC;
+	   red_out : out STD_LOGIC;
+	   blue_out : out STD_LOGIC;
+	   green_out : out STD_LOGIC;
+	   hsync_out : out STD_LOGIC;
+	   vsync_out : out STD_LOGIC;
+           hdmi_c : out  STD_LOGIC;
+           hdmi_r : out  STD_LOGIC;
+           hdmi_g : out  STD_LOGIC;
+           hdmi_b : out  STD_LOGIC);
+end hp_lcd_driver;
+
+architecture Behavioral of hp_lcd_driver is
+
+signal wr_addr : std_logic_vector(addr_width-1 downto 0);
+signal wr_data : std_logic_vector(video_width-1 downto 0);
+signal wr_en : std_logic_vector(0 downto 0);
+
+signal rd_addr : std_logic_vector(addr_width-1 downto 0);
+signal rd_data : std_logic_vector(video_width-1 downto 0);
+
+signal red : std_logic_vector(7 downto 0);
+signal green : std_logic_vector(7 downto 0);
+signal blue : std_logic_vector(7 downto 0);
+
+
+signal i_clk : std_logic;
+signal o_clk_5: std_logic;
+signal o_clk: std_logic;
+signal o_clk_n: std_logic;
+
+signal clk_50m : std_logic;
+
+signal sys_rst : std_logic;
+
+begin
+
+sys_rst <= not sys_rst_n;
+
+clk_buf: BUFG
+port map (
+   I => clk_50m_in,
+   O => clk_50m
+);
+
+
+
+ipll:entity  work.pll_50_80
+	port map (
+		reset => sys_rst,
+		clk_50_in => clk_50m,
+		clk_80_out => i_clk
+	);
+
+opll:entity  work.pll_50_91_18
+	port map (
+		reset => sys_rst,
+		clk_50_in => clk_50m,
+		clk_91_666_out => o_clk_5,
+		clk_18_333_out => o_clk
+	);
+
+input0: entity work.input_stage
+		generic map(
+		video_width => video_width,
+		addr_width => addr_width,
+		clk_multiple => 4, 
+		phase => 2,
+		h_front_porch => 208,
+		h_active => 592,
+		v_front_porch => 2,
+		v_active => 384,
+		h_stride => 384,
+		v_stride => 1
+		)
+	port map (
+	  sys_rst_n => sys_rst_n,
+	clk => i_clk,
+	  video_in => video,
+	  hsync_in => hsync_in,
+	  vsync_in => vsync_in,
+	  video_out => wr_data,
+	  addr_out => wr_addr,
+	  wren_out => wr_en(0));
+
+vram0: entity work.vram
+	port map (
+	clka => i_clk,
+	wea => wr_en,
+	addra => wr_addr,
+	dina => wr_data,
+	clkb => o_clk,
+	addrb => rd_addr,
+	doutb => rd_data
+);
+
+
+output0: entity work.output_stage
+
+-- works at 60Hz xrandr --newmode "$M"  18.24   384  400  440  600   592  593  596  613  -HSync +Vsync
+	generic map (
+		addr_width => addr_width,
+		h_active => 384,
+		h_sync_start => 400,
+		h_sync_end => 440,
+		h_total =>600,
+		v_active=>592,
+		v_sync_start=>593,
+		v_sync_end=>596,
+		v_total=>614,
+		h_stride => 1,
+		v_stride => 384
+	)
+	port map(
+		clk => o_clk,
+		sys_rst_n => sys_rst_n,
+	  	vsync_in => vsync_in,
+		red_in => red,
+		green_in=>green,
+		blue_in => blue,
+		addr_out => rd_addr,
+		red_out => red_out,
+		green_out => green_out,
+		blue_out => blue_out,
+		hsync_out => hsync_out,
+		vsync_out => vsync_out,
+		hdmi_r => hdmi_r,
+		hdmi_g => hdmi_g,
+		hdmi_b => hdmi_b,
+		hdmi_c => hdmi_c
+	);
+	
+
+end Behavioral;
+
diff --git a/spartan6/hp_lcd_driver/input_formatter.vhdl b/spartan6/hp_lcd_driver/input_formatter.vhdl
new file mode 100644
index 0000000..681795f
--- /dev/null
+++ b/spartan6/hp_lcd_driver/input_formatter.vhdl
@@ -0,0 +1,110 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+ENTITY input_formatter IS
+    generic (
+	     addr_width      : natural := 17;
+		clk_multiple : natural := 4;
+		phase : natural := 2;
+		h_front_porch : natural := 208;
+		h_active : natural := 592;
+		v_front_porch : natural := 2;
+		v_active : natural := 384;
+		h_stride : natural := 384;
+		v_stride : natural := 1);
+	PORT
+	(
+	  sys_rst_n : in std_logic;
+	  clk : in std_logic;
+	  hsync:in std_logic;
+	  vsync: in std_logic;
+	  addr_out : out std_logic_vector(addr_width-1 downto 0);
+	  wren_out : out std_logic
+	  );
+	  
+END input_formatter;
+
+
+ARCHITECTURE beh OF input_formatter IS
+
+   signal row_addr : std_logic_vector(addr_width-1 downto 0)	;
+   signal addr : std_logic_vector(addr_width-1 downto 0)	;
+   signal wren: std_logic;
+
+ signal hsync_pe: std_logic;
+ signal hsync_ne: std_logic;
+
+ signal fp_counter:natural;
+ signal active_counter:natural;
+
+		
+begin
+
+
+    hsync_ed : entity work.edge_det
+        port map(
+            clk => clk,
+            sig => hsync,
+            pe  => hsync_pe,
+            ne  => hsync_ne);
+
+
+
+addr<= (others => '0');
+
+addr_out <= addr;
+wren_out <= '0';
+
+
+---- horizontal state machine
+--
+--	process (sys_rst_n,p_clk,d_hsync,d_vsync)  begin
+--	if sys_rst_n = '0' then
+--		row_addr<=(others =>'0');
+--		addr<=(others =>'0');
+--		p_clk_div<=p_clk_multiple;
+--		active_counter <=0;
+--		fp_counter <=0;
+--	elsif rising_edge(p_clk) then
+--		if d_vsync='1' then
+--			row_addr<=(others => '0');
+--			addr<=(others => '0');
+--			fp_counter <= front_porch;
+--			active_counter <=hres;
+--			p_clk_div <=p_clk_multiple;
+--            	elsif pe_gsync ='1' then
+--			row_addr <= std_logic_vector(unsigned(row_addr)+1);
+--		elsif ne_hsync='1' then
+--			fp_counter <= front_porch;
+--			active_counter <=hres;
+--			p_clk_div <=p_clk_multiple;
+--			addr<=row_addr;
+--		elsif fp_counter /= 0 then
+--			fp_counter <= fp_counter -1;
+--		elsif active_counter /= 0 then	
+--			if p_clk_div = 0 then
+--				p_clk_div <=p_clk_multiple;
+--				active_counter <= active_counter  -1;
+--		   		addr <= std_logic_vector(unsigned(addr)+vres);
+--			else 
+--				p_clk_div <= p_clk_div - 1;
+--			end if;
+--		else 
+--			p_clk_div <=p_clk_multiple;
+--		end if;
+--	end if;
+--	end process;
+--			
+--
+--        wren <= '1' when p_clk_div=2 else '0';
+--
+--	addr_out <= addr;
+--        video_out <= (s_video, s_bright);
+--        wren_out <= wren;
+--
+--        p_clk_out <= p_clk;
+--
+
+end beh;
diff --git a/spartan6/hp_lcd_driver/input_stage.vhdl b/spartan6/hp_lcd_driver/input_stage.vhdl
new file mode 100644
index 0000000..7211cf7
--- /dev/null
+++ b/spartan6/hp_lcd_driver/input_stage.vhdl
@@ -0,0 +1,121 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+ENTITY input_stage IS
+    generic (debounce_stages : natural := 2;
+             sync_stages     : natural := 2;
+	     video_width     : natural := 2;
+	     addr_width      : natural := 17;
+		clk_multiple : natural := 4; 
+		phase : natural := 2;
+		h_front_porch : natural := 208;
+		h_active : natural := 592;
+		v_front_porch : natural := 2;
+		v_active : natural := 384;
+		h_stride : natural := 384;
+		v_stride : natural := 1);
+	PORT
+	(
+	  clk : in std_logic;
+	  sys_rst_n : in std_logic;
+
+	  video_in:in std_logic_vector(video_width -1 downto 0);
+
+	  hsync_in:in std_logic;
+	  vsync_in: in std_logic;
+
+	  video_out: out std_logic_vector(video_width-1  downto 0);
+	  addr_out : out std_logic_vector(addr_width - 1 downto 0);
+	  wren_out : out std_logic
+	  );
+END input_stage;
+
+
+ARCHITECTURE beh OF input_stage IS
+
+ signal s_hsync: std_logic;
+ signal d_hsync: std_logic;
+
+ signal s_vsync: std_logic;
+ signal d_vsync: std_logic;
+
+ signal s_video: std_logic_vector(video_width-1 downto 0);
+
+ signal addr: std_logic_vector(addr_width - 1 downto 0);
+ signal wren : std_logic;
+
+begin
+
+    video_sync_for: for b in 0 to video_width -1 generate
+      sync: entity work.synchronizer
+		generic map(stages => sync_stages + debounce_stages)
+		port map (
+			clk=>clk,
+			i => video_in(b),
+			o =>s_video(b)
+			);
+    end generate;
+
+   video_out <= s_video;
+
+
+    hsync_sync: entity work.synchronizer
+		generic map(stages => sync_stages)
+		port map (
+			clk=>clk,
+			i => hsync_in,
+			o =>s_hsync
+			);
+
+    vsync_sync: entity work.synchronizer
+		generic map(stages => sync_stages  )
+		port map (
+			clk=>clk,
+			i => vsync_in,
+			o =>s_vsync
+			);
+
+    hsync_debounce : entity work.debounce
+        generic map(stages => debounce_stages)
+        port map(
+            clk => clk,
+            i   => s_hsync,
+            o   => d_hsync);
+
+
+
+    vsync_debounce : entity work.debounce
+        generic map(stages => debounce_stages)
+        port map(
+            clk => clk,
+            i   => s_vsync,
+            o   => d_vsync);
+
+
+    input_formatter: entity work.input_formatter
+	generic map(
+		-- 20.000 592 608 680 816 384 385 400 402
+		addr_width => addr_width,
+		clk_multiple => clk_multiple,
+		phase => phase,
+		h_front_porch => h_front_porch,
+		h_active => h_active,
+		v_front_porch => v_front_porch,
+		v_active => v_active,
+		h_stride => h_stride,
+		v_stride => v_stride)
+	port map (
+	  	sys_rst_n => sys_rst_n,
+		clk => clk,
+		hsync => d_hsync,
+		vsync => d_vsync,
+		addr_out => addr,
+		wren_out => wren
+	);
+
+
+	addr_out <= addr;
+	wren_out <= wren;
+
+end beh;
diff --git a/spartan6/hp_lcd_driver/output_analog.vhdl b/spartan6/hp_lcd_driver/output_analog.vhdl
new file mode 100644
index 0000000..30e7d97
--- /dev/null
+++ b/spartan6/hp_lcd_driver/output_analog.vhdl
@@ -0,0 +1,80 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+ENTITY output_analog IS
+	PORT
+	(
+	  clk : in std_logic;
+	  sys_rst_n : in std_logic;
+
+	  red_in: in std_logic;
+	  green_in: in std_logic;
+	  blue_in: in std_logic;
+	  hsync_in: in std_logic;
+	  vsync_in: in std_logic;
+	  blank_in: in std_logic;
+
+	  red_out:out std_logic;
+	  green_out:out std_logic;
+	  blue_out:out std_logic;
+	  hsync_out:out std_logic;
+	  vsync_out:out std_logic
+	  );
+END output_analog;
+
+
+ARCHITECTURE beh OF output_analog IS
+
+
+ signal red_r : std_logic;
+ signal green_r : std_logic;
+ signal blue_r : std_logic;
+
+ signal hsync_r : std_logic;
+ signal vsync_r : std_logic;
+ signal blank_r : std_logic;
+
+
+
+begin
+
+process (sys_rst_n,clk) begin
+if sys_rst_n ='0' then
+	red_r<='0';
+	green_r<='0';
+	blue_r<='0';
+	hsync_r<='0';
+	vsync_r<='0';
+	blank_r <= '0';
+elsif rising_edge(clk) then
+	red_r<=red_in;
+	green_r<=green_in;
+	blue_r<=blue_in;
+	hsync_r<=hsync_in;
+	vsync_r<=vsync_in;
+	blank_r <=blank_in;
+
+end if;
+end process;
+
+
+process (sys_rst_n,clk) begin
+if sys_rst_n ='0' then
+	red_out<='0';
+	green_out<='0';
+	blue_out<='0';
+	hsync_out<='0';
+	vsync_out<='0';
+elsif rising_edge(clk) then
+	red_out<=red_r and not blank_r;
+	green_out<=green_r and not blank_r;
+	blue_out<=blue_r and not blank_r;
+	hsync_out<=hsync_r;
+	vsync_out<=vsync_r;
+end if;
+end process;
+
+
+end beh;
diff --git a/spartan6/hp_lcd_driver/output_formatter.vhdl b/spartan6/hp_lcd_driver/output_formatter.vhdl
new file mode 100644
index 0000000..8eff2de
--- /dev/null
+++ b/spartan6/hp_lcd_driver/output_formatter.vhdl
@@ -0,0 +1,125 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+
+
+ENTITY output_formatter IS
+    generic ( addr_width      : natural := 17;
+		h_front_porch : natural := 208;
+		h_active :natural := 384;
+		h_sync_start :natural := 400;
+		h_sync_end :natural := 440;
+		h_total :natural :=600;
+		v_active :natural :=592;
+		v_sync_start:natural:=593;
+		v_sync_end:natural :=596;
+		v_total:natural :=614;
+		h_stride :natural := 1;
+		v_stride :natural := 384
+	);
+	port (
+	  	sys_rst_n : in std_logic;
+		clk : in std_logic;
+		vsync_in : in std_logic;
+		addr_out : out std_logic_vector(addr_width -1 downto 0);
+		blank_out  : out std_logic;
+		vsync_out  : out std_logic;
+		hsync_out  : out std_logic
+	);
+END output_formatter;
+
+
+ARCHITECTURE beh OF output_formatter IS
+
+   signal row_addr : std_logic_vector(addr_width-1 downto 0)	;
+   signal addr : std_logic_vector(addr_width-1 downto 0)	;
+
+   signal vsync_in_ne: std_logic;
+
+   signal h:natural;
+   signal v:natural;
+
+
+   signal blank:std_logic;
+   signal vblank:std_logic;
+   signal vsync:std_logic;
+   signal hsync:std_logic;
+
+		
+begin
+
+    vsync_ed : entity work.edge_det
+        port map(
+            clk => clk,
+            sig => vsync_in,
+            ne  => vsync_in_ne);
+
+    process (clk, vsync_in_ne,sys_rst_n) begin
+	if sys_rst_n='0' then 
+		h<=0;	
+		v<=0;
+	elsif rising_edge(clk) then
+		if h /= (h_total-1) then
+		  h<=h+1;
+		else 
+		  if v /= (v_total-1) then 
+		    v<=v+1;
+		    h<=0;
+		  elsif vsync_in_ne='1' then
+			h<=0;
+			v<=0;
+		  end if;
+	     end if;
+	end if;
+    end process;
+		
+
+    process (clk,h,h,sys_rst_n) begin
+	if sys_rst_n='0' then 
+		row_addr <=(others =>'0');
+		addr <=(others =>'0');
+		blank <='1';
+		vsync <='0';
+		hsync <='0';
+	elsif rising_edge(clk) then
+
+		if h=0 then
+			if v= 0 then
+				row_addr <=(others =>'0');
+				addr <=(others =>'0');
+				blank<='0';
+				vblank <='0';
+			elsif v=v_active then
+				vblank<='1';
+			elsif v=v_sync_start then
+				vsync<='1';
+			elsif v=v_sync_end then
+				vsync<='0';
+			else
+				blank <=vblank;
+				row_addr <= std_logic_vector(unsigned(row_addr)+v_stride);
+				addr <=row_addr;
+			end if;		
+		elsif h=h_active then
+			blank<='1';
+		elsif h=h_sync_start then
+			hsync<='1';
+		elsif h=h_sync_end then
+			hsync<='0';
+		else
+			addr <= std_logic_vector(unsigned(addr)+h_stride);
+		end if;
+	end if;
+      end process;
+			
+
+      addr_out <= addr;
+      blank_out <= blank;
+      hsync_out <= hsync;
+      vsync_out <= vsync;
+
+end beh;
+
+
+	
diff --git a/spartan6/hp_lcd_driver/output_stage.vhdl b/spartan6/hp_lcd_driver/output_stage.vhdl
new file mode 100644
index 0000000..7b977a4
--- /dev/null
+++ b/spartan6/hp_lcd_driver/output_stage.vhdl
@@ -0,0 +1,153 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+Library UNISIM;
+use UNISIM.vcomponents.all;
+
+
+ENTITY output_stage IS
+    generic (debounce_stages : natural := 2;
+             sync_stages     : natural := 2;
+	     addr_width      : natural := 17;
+		h_front_porch : natural := 208;
+		h_active :natural := 384;
+		h_sync_start :natural := 400;
+		h_sync_end :natural := 440;
+		h_total :natural:=600;
+		v_active :natural :=592;
+		v_sync_start:natural:=593;
+		v_sync_end:natural :=596;
+		v_total:natural :=614;
+		h_stride :natural := 1;
+		v_stride :natural := 384
+	);
+	PORT
+	(
+	  clk : in std_logic;
+	  sys_rst_n : in std_logic;
+
+	  vsync_in: in std_logic;
+
+	  addr_out : out std_logic_vector(addr_width - 1 downto 0);
+
+	  red_in:in std_logic_vector(7 downto 0);
+	  green_in:in std_logic_vector(7 downto 0);
+	  blue_in:in std_logic_vector(7 downto 0);
+
+
+	  red_out:out std_logic;
+	  green_out:out std_logic;
+	  blue_out:out std_logic;
+	  hsync_out:out std_logic;
+	  vsync_out:out std_logic;
+	  
+	  hdmi_c: out std_logic;
+	  hdmi_r: out std_logic;
+	  hdmi_g: out std_logic;
+	  hdmi_b: out std_logic
+	  );
+END output_stage;
+
+
+ARCHITECTURE beh OF output_stage IS
+
+ signal n_clk : std_logic;
+
+ signal s_vsync_in: std_logic;
+ signal d_vsync_in: std_logic;
+
+ signal blank: std_logic;
+
+ signal hsync: std_logic;
+ signal vsync: std_logic;
+
+ signal addr: std_logic_vector(addr_width - 1 downto 0);
+
+ begin
+
+
+    vsync_sync: entity work.synchronizer
+		generic map(stages => sync_stages  )
+		port map (
+			clk=>clk,
+			i => vsync_in,
+			o =>s_vsync_in
+			);
+
+    vsync_debounce : entity work.debounce
+        generic map(stages => debounce_stages)
+        port map(
+            clk => clk,
+            i   => s_vsync_in,
+            o   => d_vsync_in);
+
+
+    output_formatter: entity work.output_formatter
+	generic map(
+		addr_width => addr_width,
+		h_active  => h_active,
+		h_sync_start  => h_sync_start,
+		h_sync_end  => h_sync_end,
+		h_total  => h_total,
+		v_active => v_active,
+		v_sync_start => v_sync_start,
+		v_sync_end => v_sync_end,
+		v_total => v_total,
+		h_stride  => h_stride,
+		v_stride  => v_stride)
+	port map (
+	  	sys_rst_n => sys_rst_n,
+		clk => clk,
+		vsync_in => d_vsync_in,
+		addr_out => addr,
+		blank_out => blank,
+		vsync_out => vsync,
+		hsync_out => hsync
+	);
+
+
+	addr_out <= addr;
+
+
+    output_analog : entity work.output_analog
+	port map(
+	  	sys_rst_n => sys_rst_n,
+		clk => clk,
+
+		hsync_in => hsync,
+		vsync_in => vsync,
+		blank_in => blank,
+		red_in => green_in(7),
+		green_in => green_in(6),
+		blue_in => blue_in(7),
+
+		red_out => red_out,
+		green_out => green_out,
+		blue_out => blue_out,
+		hsync_out =>  hsync_out,
+		vsync_out => vsync_out
+	);
+
+
+
+
+n_clk <= not clk;
+hdmi_r <= hsync;
+hdmi_g <= vsync;
+hdmi_b <= green_in(7);
+
+
+
+o_clk_buf: ODDR2
+port map (
+   D0 => '1',
+   D1 => '0',
+   C0 => clk,
+   C1 => n_clk,
+   CE =>'1',
+   Q => hdmi_c
+);
+
+
+end beh;
diff --git a/spartan6/hp_lcd_driver/pll_50_80.xco b/spartan6/hp_lcd_driver/pll_50_80.xco
new file mode 100644
index 0000000..b175ef8
--- /dev/null
+++ b/spartan6/hp_lcd_driver/pll_50_80.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Sat Apr 26 17:50:20 2025
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=clk_80_out
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=80.000
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=100.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=pll_50_80
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=5
+CSET dcm_clkfx_multiply=8
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=lin
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=4
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=10.000
+CSET pll_clkout0_divide=1
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=1
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50.000
+CSET prim_in_jitter=0.010
+CSET prim_source=No_buffer
+CSET primary_port=clk_50_in
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: fe735cf8
diff --git a/spartan6/hp_lcd_driver/pll_50_91_18.xco b/spartan6/hp_lcd_driver/pll_50_91_18.xco
new file mode 100644
index 0000000..1d02dba
--- /dev/null
+++ b/spartan6/hp_lcd_driver/pll_50_91_18.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Sat Apr 26 17:51:02 2025
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=clk_91_666_out
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=clk_18_333_out
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=91.667
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=18.333
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=true
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=pll_50_91_18
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=2X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK2X
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=6
+CSET dcm_clkfx_multiply=11
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=2
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=lin
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=11
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=20.000
+CSET pll_clkout0_divide=6
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=30
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50.000
+CSET prim_in_jitter=0.010
+CSET prim_source=No_buffer
+CSET primary_port=clk_50_in
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: 95fa1f8c
diff --git a/spartan6/hp_lcd_driver/scripts/vhdl-pretty b/spartan6/hp_lcd_driver/scripts/vhdl-pretty
new file mode 100755
index 0000000..c514b85
--- /dev/null
+++ b/spartan6/hp_lcd_driver/scripts/vhdl-pretty
@@ -0,0 +1,60 @@
+#! /bin/sh
+":"; exec emacs --no-site-file --script "$0" -- "$0" "$@" # -*-emacs-lisp-*-
+; vim: noai:ts=4:sw=4:syntax=lisp
+
+(setq arg0 (file-truename (car (cdr argv))))
+(setq args (cdr (cdr argv)))
+(setq argv nil)
+
+; Parse the command line arguments,
+;  --xxx           -> ("xxx" t)
+;  --no-xxx        -> ("xxx" nil)
+;  --xxx=123       -> ("xxx" 123)
+;  --xxx=abc       -> ("xxx" "abc")
+;  --xxx='abc 123' -> ("xxx" "abc 123")
+;  --xxx=abc=123   -> ("xxx" "abc=123")
+(setq args
+  (mapcar
+    (lambda (arg)
+      (cond
+        ((string-match "^--no-\\([^=]*\\)$" arg)
+          (list (intern (match-string 1 arg)) nil))
+        ((string-match "^--\\([^=]*\\)$" arg)
+          (list (intern (match-string 1 arg)) t))
+        ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\([0-9]+\\)\\2$" arg)
+          (list (intern (match-string 1 arg)) (string-to-number (match-string 3 arg))))
+        ((string-match "^--\\([^=]*\\)=\\([\"']?\\)\\(.+?\\)\\2$" arg)
+          (list (intern (match-string 1 arg)) (match-string 3 arg)))
+        (t nil)
+      ))
+    args))
+
+; Read stdin into buffer
+(defun insert-standard-input ()
+  "insert contents from standard input"
+  (condition-case nil
+      (let (line)
+        (while (setq line (read-from-minibuffer ""))
+          (insert line "\n")))
+    (error nil)))
+
+(insert-standard-input)
+(goto-char (point-min))
+
+; Load library
+(setq basedir (concat (file-name-directory arg0) "vhdl-mode"))
+(setq load-path (cons basedir load-path))
+(load-library "vhdl-mode")
+
+; Default customisation
+(vhdl-set-style "IEEE")
+
+; Customisation from cmdline
+(mapc (lambda (arg) (customize-set-variable (car arg) (car (cdr arg)))) args)
+
+; Turn on mode and beautify
+(vhdl-mode)
+(vhdl-beautify-region (point-min) (point-max))
+
+; Output buffer to stdout
+(princ (buffer-string))
diff --git a/spartan6/hp_lcd_driver/synchronizer.vhdl b/spartan6/hp_lcd_driver/synchronizer.vhdl
new file mode 100644
index 0000000..99618b9
--- /dev/null
+++ b/spartan6/hp_lcd_driver/synchronizer.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity synchronizer is
+    generic (stages : natural := 2);
+    port (clk : in  std_logic;
+          i   : in  std_logic;
+          o   : out std_logic);
+end synchronizer;
+
+architecture Behavioral of synchronizer is
+    signal flipflops                 : std_logic_vector(stages-1 downto 0) := (others => '0');
+    attribute ASYNC_REG              : string;
+    attribute ASYNC_REG of flipflops : signal is "true";
+begin
+
+    o <= flipflops(flipflops'high);
+
+    clk_proc : process(clk,flipflops,i)
+    begin
+        if rising_edge(clk) then
+            flipflops <= flipflops(flipflops'high-1 downto 0) & i;
+        end if;
+    end process;
+
+end Behavioral;