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-rw-r--r--os/hal/platforms/STM32/SPIv2/spi_lld.c12
-rw-r--r--os/hal/platforms/STM32/can_lld.c12
-rw-r--r--os/hal/platforms/STM32/icu_lld.c4
-rw-r--r--os/hal/platforms/STM32/pwm_lld.c6
-rw-r--r--os/hal/platforms/STM32F30x/adc_lld.c11
-rw-r--r--os/hal/platforms/STM32F30x/stm32_dma.c2
6 files changed, 20 insertions, 27 deletions
diff --git a/os/hal/platforms/STM32/SPIv2/spi_lld.c b/os/hal/platforms/STM32/SPIv2/spi_lld.c
index 712d824f6..3cbcc0fc0 100644
--- a/os/hal/platforms/STM32/SPIv2/spi_lld.c
+++ b/os/hal/platforms/STM32/SPIv2/spi_lld.c
@@ -221,12 +221,12 @@ void spi_lld_start(SPIDriver *spip) {
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- osalDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI1_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- osalDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI1(FALSE);
}
#endif
@@ -237,12 +237,12 @@ void spi_lld_start(SPIDriver *spip) {
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- osalDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI2_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- osalDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI2(FALSE);
}
#endif
@@ -253,12 +253,12 @@ void spi_lld_start(SPIDriver *spip) {
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_rx_interrupt,
(void *)spip);
- osalDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(spip->dmatx,
STM32_SPI_SPI3_IRQ_PRIORITY,
(stm32_dmaisr_t)spi_lld_serve_tx_interrupt,
(void *)spip);
- osalDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableSPI3(FALSE);
}
#endif
diff --git a/os/hal/platforms/STM32/can_lld.c b/os/hal/platforms/STM32/can_lld.c
index 2febf5bc9..a53a8fe27 100644
--- a/os/hal/platforms/STM32/can_lld.c
+++ b/os/hal/platforms/STM32/can_lld.c
@@ -404,8 +404,7 @@ void can_lld_start(CANDriver *canp) {
#if STM32_CAN_USE_CAN2
if (&CAND2 == canp) {
- osalDbgAssert(CAND1.state != CAN_STOP,
- "can_lld_start(), #1", "CAN1 must be started");
+ osalDbgAssert(CAND1.state != CAN_STOP, "CAN1 must be started");
nvicEnableVector(STM32_CAN2_TX_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
nvicEnableVector(STM32_CAN2_RX0_NUMBER, STM32_CAN_CAN2_IRQ_PRIORITY);
@@ -447,8 +446,7 @@ void can_lld_stop(CANDriver *canp) {
if (&CAND1 == canp) {
#if STM32_CAN_USE_CAN2
- osalDbgAssert(CAND2.state == CAN_STOP,
- "can_lld_stop(), #1", "CAN2 must be stopped");
+ osalDbgAssert(CAND2.state == CAN_STOP, "CAN2 must be stopped");
#endif
CAN1->MCR = 0x00010002; /* Register reset value. */
@@ -690,12 +688,10 @@ void canSTM32SetFilters(uint32_t can2sb, uint32_t num, const CANFilter *cfp) {
(num < STM32_CAN_MAX_FILTERS));
#if STM32_CAN_USE_CAN1
- osalDbgAssert(CAND1.state == CAN_STOP,
- "canSTM32SetFilters(), #1", "invalid state");
+ osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
#endif
#if STM32_CAN_USE_CAN2
- osalDbgAssert(CAND2.state == CAN_STOP,
- "canSTM32SetFilters(), #2", "invalid state");
+ osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
#endif
can_lld_set_filters(can2sb, num, cfp);
diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c
index 149231aa3..73699c637 100644
--- a/os/hal/platforms/STM32/icu_lld.c
+++ b/os/hal/platforms/STM32/icu_lld.c
@@ -392,7 +392,7 @@ void icu_lld_start(ICUDriver *icup) {
osalDbgAssert((icup->config->channel == ICU_CHANNEL_1) ||
(icup->config->channel == ICU_CHANNEL_2),
- "icu_lld_start(), #1", "invalid input");
+ "invalid input");
if (icup->state == ICU_STOP) {
/* Clock activation and timer reset.*/
@@ -469,7 +469,7 @@ void icu_lld_start(ICUDriver *icup) {
psc = (icup->clock / icup->config->frequency) - 1;
osalDbgAssert((psc <= 0xFFFF) &&
((psc + 1) * icup->config->frequency) == icup->clock,
- "icu_lld_start(), #1", "invalid frequency");
+ "invalid frequency");
icup->tim->PSC = (uint16_t)psc;
icup->tim->ARR = 0xFFFF;
diff --git a/os/hal/platforms/STM32/pwm_lld.c b/os/hal/platforms/STM32/pwm_lld.c
index a8850924f..c3109beee 100644
--- a/os/hal/platforms/STM32/pwm_lld.c
+++ b/os/hal/platforms/STM32/pwm_lld.c
@@ -488,9 +488,9 @@ void pwm_lld_start(PWMDriver *pwmp) {
/* Timer configuration.*/
psc = (pwmp->clock / pwmp->config->frequency) - 1;
- chDbgAssert((psc <= 0xFFFF) &&
- ((psc + 1) * pwmp->config->frequency) == pwmp->clock,
- "pwm_lld_start(), #1", "invalid frequency");
+ osalDbgAssert((psc <= 0xFFFF) &&
+ ((psc + 1) * pwmp->config->frequency) == pwmp->clock,
+ "invalid frequency");
pwmp->tim->PSC = (uint16_t)psc;
pwmp->tim->ARR = (uint16_t)(pwmp->period - 1);
pwmp->tim->CR2 = pwmp->config->cr2;
diff --git a/os/hal/platforms/STM32F30x/adc_lld.c b/os/hal/platforms/STM32F30x/adc_lld.c
index 768420c52..d516cf21b 100644
--- a/os/hal/platforms/STM32F30x/adc_lld.c
+++ b/os/hal/platforms/STM32F30x/adc_lld.c
@@ -147,14 +147,12 @@ static void adc_lld_analog_off(ADCDriver *adcp) {
*/
static void adc_lld_calibrate(ADCDriver *adcp) {
- osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #1",
- "invalid register state");
+ osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
adcp->adcm->CR |= ADC_CR_ADCAL;
while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
;
#if STM32_ADC_DUAL_MODE
- osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "adc_lld_calibrate(), #2",
- "invalid register state");
+ osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
adcp->adcs->CR |= ADC_CR_ADCAL;
while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
;
@@ -377,7 +375,7 @@ void adc_lld_start(ADCDriver *adcp) {
STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
- osalDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableADC12(FALSE);
}
#endif /* STM32_ADC_USE_ADC1 */
@@ -389,7 +387,7 @@ void adc_lld_start(ADCDriver *adcp) {
STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
(void *)adcp);
- osalDbgAssert(!b, "adc_lld_start(), #2", "stream already allocated");
+ osalDbgAssert(!b, "stream already allocated");
rccEnableADC34(FALSE);
}
#endif /* STM32_ADC_USE_ADC2 */
@@ -459,7 +457,6 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
const ADCConversionGroup *grpp = adcp->grpp;
osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
- "adc_lld_start_conversion(), #1",
"odd number of channels in dual mode");
/* Calculating control registers values.*/
diff --git a/os/hal/platforms/STM32F30x/stm32_dma.c b/os/hal/platforms/STM32F30x/stm32_dma.c
index 430a9f667..eb73f1b37 100644
--- a/os/hal/platforms/STM32F30x/stm32_dma.c
+++ b/os/hal/platforms/STM32F30x/stm32_dma.c
@@ -427,7 +427,7 @@ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
/* Check if the streams is not taken.*/
osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
- "dmaStreamRelease(), #1", "not allocated");
+ "not allocated");
/* Disables the associated IRQ vector.*/
nvicDisableVector(dmastp->vector);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 00:41:39 +0000