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| author | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-03-11 11:46:08 +0000 |
|---|---|---|
| committer | Giovanni Di Sirio <gdisirio@gmail.com> | 2019-03-11 11:46:08 +0000 |
| commit | 2c4e1d1763864d547a3ca37cd079819e047982dc (patch) | |
| tree | dd7b857b2391b9e55a6d2c78d3c8b76bb358cb54 /os/hal/ports/STM32/STM32H7xx | |
| parent | 14eea36396e50de3f4f54a53862b130162449821 (diff) | |
| download | ChibiOS-2c4e1d1763864d547a3ca37cd079819e047982dc.tar.gz ChibiOS-2c4e1d1763864d547a3ca37cd079819e047982dc.tar.bz2 ChibiOS-2c4e1d1763864d547a3ca37cd079819e047982dc.zip | |
Re-introduced missing chGuardedPoolGetCounterI().
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12687 27425a3e-05d8-49a3-a47f-9c15f0e5edd8
Diffstat (limited to 'os/hal/ports/STM32/STM32H7xx')
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/hal_lld.c | 2 | ||||
| -rw-r--r-- | os/hal/ports/STM32/STM32H7xx/hal_lld.h | 6 |
2 files changed, 4 insertions, 4 deletions
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c index 60ce00310..df3e2f478 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -206,7 +206,7 @@ void stm32_clock_init(void) { /* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data
read corruption.
AXI->TARG7_FN_MOD.*/
- *((volatile uint32_t *)0x51000000 + 0x1108 + 0x7000) = 0x00000001U;
+ *((volatile uint32_t *)(0x51000000 + 0x1108 + 0x7000)) = 0x00000001U;
#endif
/* PWR initialization.*/
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h index 926630588..2c6e75b6b 100644 --- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -494,9 +494,9 @@ #define STM32_SAI4ASEL_PER_CK RCC_D3CCIPR_SAI4ASEL_VALUE(4U)
#define STM32_ADCSEL_PLL2_P_CK RCC_D3CCIPR_ADCSEL_VALUE(0U)
-#define STM32_ADCSEL_PLL3_R_CK RCC_D3CCIPR_ADCSEL_VALUE(0U)
-#define STM32_ADCSEL_PER_CK RCC_D3CCIPR_ADCSEL_VALUE(0U)
-#define STM32_ADCSEL_DISABLE RCC_D3CCIPR_ADCSEL_VALUE(0U)
+#define STM32_ADCSEL_PLL3_R_CK RCC_D3CCIPR_ADCSEL_VALUE(1U)
+#define STM32_ADCSEL_PER_CK RCC_D3CCIPR_ADCSEL_VALUE(2U)
+#define STM32_ADCSEL_DISABLE RCC_D3CCIPR_ADCSEL_VALUE(3U)
#define STM32_LPTIM345SEL_PCLK4 RCC_D3CCIPR_LPTIM345SEL_VALUE(0U)
#define STM32_LPTIM345SEL_PLL2_P_CK RCC_D3CCIPR_LPTIM345SEL_VALUE(1U)
|