Re-introduced missing chGuardedPoolGetCounterI().

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/stable_19.1.x@12687 27425a3e-05d8-49a3-a47f-9c15f0e5edd8

5 files changed, 24 insertions, 6 deletions

diff --git a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
index 1991ccb5b..790af8a49 100644
--- a/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
+++ b/os/hal/ports/STM32/LLD/ADCv3/hal_adc_lld.c
@@ -496,7 +496,7 @@ void adc_lld_init(void) {
 #if defined(ADC3_4_COMMON)

   ADCD3.adcc = ADC3_4_COMMON;

 #elif defined(ADC123_COMMON)

-  ADCD1.adcc = ADC123_COMMON;

+  ADCD3.adcc = ADC123_COMMON;

 #else

   ADCD3.adcc = ADC3_COMMON;

 #endif

diff --git a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
index 0015258d9..a5d2a5cb7 100644
--- a/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
+++ b/os/hal/ports/STM32/LLD/SDMMCv1/hal_sdc_lld.c
@@ -503,7 +503,7 @@ void sdc_lld_stop(SDCDriver *sdcp) {
     sdcp->sdmmc->DTIMER = 0;

 

     /* DMA stream released.*/

-    dmaStreamRelease(sdcp->dma);

+    dmaStreamFreeI(sdcp->dma);

     sdcp->dma = NULL;

 

     /* Clock deactivation.*/

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
index b99ebdde8..c00c973dd 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_st_lld.c
@@ -42,6 +42,9 @@
 #if !STM32_HAS_TIM2

 #error "TIM2 not present in the selected device"

 #endif

+#if defined(STM32_TIM2_IS_USED)

+#error "ST requires TIM2 but the timer is already used"

+#endif

 #if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM2_IS_32BITS

 #error "TIM2 is not a 32bits timer"

 #endif

@@ -64,6 +67,9 @@
 #if !STM32_HAS_TIM3

 #error "TIM3 not present in the selected device"

 #endif

+#if defined(STM32_TIM3_IS_USED)

+#error "ST requires TIM3 but the timer is already used"

+#endif

 #if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM3_IS_32BITS

 #error "TIM3 is not a 32bits timer"

 #endif

@@ -86,6 +92,9 @@
 #if !STM32_HAS_TIM4

 #error "TIM4 not present in the selected device"

 #endif

+#if defined(STM32_TIM4_IS_USED)

+#error "ST requires TIM4 but the timer is already used"

+#endif

 #if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM4_IS_32BITS

 #error "TIM4 is not a 32bits timer"

 #endif

@@ -108,6 +117,9 @@
 #if !STM32_HAS_TIM5

 #error "TIM5 not present in the selected device"

 #endif

+#if defined(STM32_TIM5_IS_USED)

+#error "ST requires TIM5 but the timer is already used"

+#endif

 #if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM5_IS_32BITS

 #error "TIM5 is not a 32bits timer"

 #endif

@@ -130,6 +142,9 @@
 #if !STM32_HAS_TIM21

 #error "TIM21 not present in the selected device"

 #endif

+#if defined(STM32_TIM21_IS_USED)

+#error "ST requires TIM21 but the timer is already used"

+#endif

 #if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM21_IS_32BITS

 #error "TIM21 is not a 32bits timer"

 #endif

@@ -144,6 +159,9 @@
 #if !STM32_HAS_TIM22

 #error "TIM22 not present in the selected device"

 #endif

+#if defined(STM32_TIM22_IS_USED)

+#error "ST requires TIM22 but the timer is already used"

+#endif

 #if (OSAL_ST_RESOLUTION == 32) && !STM32_TIM22_IS_32BITS

 #error "TIM21 is not a 32bits timer"

 #endif

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index 60ce00310..df3e2f478 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -206,7 +206,7 @@ void stm32_clock_init(void) {
   /* Fix for errata 2.2.15: Reading from AXI SRAM might lead to data

      read corruption.

      AXI->TARG7_FN_MOD.*/

-  *((volatile uint32_t *)0x51000000 + 0x1108 + 0x7000) = 0x00000001U;

+  *((volatile uint32_t *)(0x51000000 + 0x1108 + 0x7000)) = 0x00000001U;

 #endif

 

   /* PWR initialization.*/

diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 926630588..2c6e75b6b 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -494,9 +494,9 @@
 #define STM32_SAI4ASEL_PER_CK           RCC_D3CCIPR_SAI4ASEL_VALUE(4U)

 

 #define STM32_ADCSEL_PLL2_P_CK          RCC_D3CCIPR_ADCSEL_VALUE(0U)

-#define STM32_ADCSEL_PLL3_R_CK          RCC_D3CCIPR_ADCSEL_VALUE(0U)

-#define STM32_ADCSEL_PER_CK             RCC_D3CCIPR_ADCSEL_VALUE(0U)

-#define STM32_ADCSEL_DISABLE            RCC_D3CCIPR_ADCSEL_VALUE(0U)

+#define STM32_ADCSEL_PLL3_R_CK          RCC_D3CCIPR_ADCSEL_VALUE(1U)

+#define STM32_ADCSEL_PER_CK             RCC_D3CCIPR_ADCSEL_VALUE(2U)

+#define STM32_ADCSEL_DISABLE            RCC_D3CCIPR_ADCSEL_VALUE(3U)

 

 #define STM32_LPTIM345SEL_PCLK4         RCC_D3CCIPR_LPTIM345SEL_VALUE(0U)

 #define STM32_LPTIM345SEL_PLL2_P_CK     RCC_D3CCIPR_LPTIM345SEL_VALUE(1U)