diff options
| author | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-04-05 07:58:29 +0000 |
|---|---|---|
| committer | gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4> | 2010-04-05 07:58:29 +0000 |
| commit | 01ce181671d28c701948c765768440a7e9a09777 (patch) | |
| tree | 72714e75f76a30ad9b34f2ec0de8b80a8001eadf /os/hal/platforms/LPC11xx | |
| parent | bc72d1c511a1732a6964aa2466264f505c86208d (diff) | |
| download | ChibiOS-01ce181671d28c701948c765768440a7e9a09777.tar.gz ChibiOS-01ce181671d28c701948c765768440a7e9a09777.tar.bz2 ChibiOS-01ce181671d28c701948c765768440a7e9a09777.zip | |
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1855 35acf78f-673a-0410-8e92-d51de3d6d3f4
Diffstat (limited to 'os/hal/platforms/LPC11xx')
| -rw-r--r-- | os/hal/platforms/LPC11xx/LPC11xx.h | 499 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/hal_lld.c | 132 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/hal_lld.h | 231 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/pal_lld.c | 95 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/pal_lld.h | 309 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/platform.dox | 76 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/platform.mk | 7 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/serial_lld.c | 286 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/serial_lld.h | 203 | ||||
| -rw-r--r-- | os/hal/platforms/LPC11xx/system_LPC11xx.h | 64 |
10 files changed, 1902 insertions, 0 deletions
diff --git a/os/hal/platforms/LPC11xx/LPC11xx.h b/os/hal/platforms/LPC11xx/LPC11xx.h new file mode 100644 index 000000000..c07fe3b47 --- /dev/null +++ b/os/hal/platforms/LPC11xx/LPC11xx.h @@ -0,0 +1,499 @@ +/**************************************************************************//**
+ * @file LPC11xx.h
+ * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
+ * NXP LPC11xx Device Series
+ * @version V1.00
+ * @date 17. November 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __LPC11xx_H__
+#define __LPC11xx_H__
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup LPC11xx_Definitions LPC11xx Definitions
+ This file defines all structures and symbols for LPC11xx:
+ - Registers and bitfields
+ - peripheral base address
+ - peripheral ID
+ - PIO definitions
+ @{
+*/
+
+
+/******************************************************************************/
+/* Processor and Core Peripherals */
+/******************************************************************************/
+/** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
+ Configuration of the Cortex-M0 Processor and Core Peripherals
+ @{
+*/
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
+
+/****** LPC13xx Specific Interrupt Numbers *******************************************************/
+ WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
+ WAKEUP1_IRQn = 1, /*!< There are 13 pins in total for LPC11xx */
+ WAKEUP2_IRQn = 2,
+ WAKEUP3_IRQn = 3,
+ WAKEUP4_IRQn = 4,
+ WAKEUP5_IRQn = 5,
+ WAKEUP6_IRQn = 6,
+ WAKEUP7_IRQn = 7,
+ WAKEUP8_IRQn = 8,
+ WAKEUP9_IRQn = 9,
+ WAKEUP10_IRQn = 10,
+ WAKEUP11_IRQn = 11,
+ WAKEUP12_IRQn = 12,
+ SSP1_IRQn = 14, /*!< SSP1 Interrupt */
+ I2C_IRQn = 15, /*!< I2C Interrupt */
+ TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
+ TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
+ TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
+ TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
+ SSP0_IRQn = 20, /*!< SSP0 Interrupt */
+ UART_IRQn = 21, /*!< UART Interrupt */
+ ADC_IRQn = 24, /*!< A/D Converter Interrupt */
+ WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
+ BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
+ EINT3_IRQn = 28, /*!< External Interrupt 3 Interrupt */
+ EINT2_IRQn = 29, /*!< External Interrupt 2 Interrupt */
+ EINT1_IRQn = 30, /*!< External Interrupt 1 Interrupt */
+ EINT0_IRQn = 31, /*!< External Interrupt 0 Interrupt */
+} IRQn_Type;
+
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/* Configuration of the Cortex-M3 Processor and Core Peripherals */
+#define __MPU_PRESENT 0 /*!< MPU present or not */
+#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+
+/*@}*/ /* end of group LPC11xx_CMSIS */
+
+
+#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
+#include "system_LPC11xx.h" /* System Header */
+
+
+/******************************************************************************/
+/* Device Specific Peripheral Registers structures */
+/******************************************************************************/
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/*------------- System Control (SYSCON) --------------------------------------*/
+/** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
+ __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
+ __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
+ __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/ ) */
+ uint32_t RESERVED0[4];
+
+ __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
+ __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
+ __IO uint32_t IRCCTRL; /*!< Offset: 0x028 IRC control (R/W) */
+ uint32_t RESERVED1[1];
+ __IO uint32_t SYSRESSTAT; /*!< Offset: 0x030 System reset status Register (R/ ) */
+ uint32_t RESERVED2[3];
+ __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
+ __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
+ uint32_t RESERVED3[10];
+
+ __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
+ __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
+ __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
+ uint32_t RESERVED4[1];
+
+ __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
+ uint32_t RESERVED5[4];
+ __IO uint32_t SSP0CLKDIV; /*!< Offset: 0x094 SSP0 clock divider (R/W) */
+ __IO uint32_t UARTCLKDIV; /*!< Offset: 0x098 UART clock divider (R/W) */
+ __IO uint32_t SSP1CLKDIV; /*!< Offset: 0x09C SSP1 clock divider (R/W) */
+ uint32_t RESERVED6[4];
+
+ __IO uint32_t SYSTICKCLKDIV; /*!< Offset: 0x0B0 SYSTICK clock divider (R/W) */
+ uint32_t RESERVED7[7];
+
+ __IO uint32_t WDTCLKSEL; /*!< Offset: 0x0D0 WDT clock source select (R/W) */
+ __IO uint32_t WDTCLKUEN; /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
+ __IO uint32_t WDTCLKDIV; /*!< Offset: 0x0D8 WDT clock divider (R/W) */
+ uint32_t RESERVED8[1];
+ __IO uint32_t CLKOUTCLKSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
+ __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
+ __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
+ uint32_t RESERVED9[5];
+
+ __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
+ __IO uint32_t PIOPORCAP1; /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
+ uint32_t RESERVED10[18];
+
+ __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
+ uint32_t RESERVED11[1];
+ __IO uint32_t SYSTCKCAL; /*!< Offset: 0x158 System tick counter calibration (R/W) */
+ uint32_t RESERVED12[41];
+
+ __IO uint32_t STARTAPRP0; /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
+ __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
+ __IO uint32_t STARTRSRP0CLR; /*!< Offset: 0x208 Start logic reset Register 0 ( /W) */
+ __IO uint32_t STARTSRP0; /*!< Offset: 0x20C Start logic status Register 0 (R/W) */
+ uint32_t RESERVED14[8];
+
+ __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
+ __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
+ __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
+ uint32_t RESERVED15[110];
+ __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
+} LPC_SYSCON_TypeDef;
+/*@}*/ /* end of group LPC11xx_SYSCON */
+
+
+/*------------- Pin Connect Block (IOCON) --------------------------------*/
+/** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PIO2_6; /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
+ uint32_t RESERVED0[1];
+ __IO uint32_t PIO2_0; /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
+ __IO uint32_t RESET_PIO0_0; /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0 (R/W) */
+ __IO uint32_t PIO0_1; /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
+ __IO uint32_t PIO1_8; /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
+ uint32_t RESERVED1[1];
+ __IO uint32_t PIO0_2; /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
+
+ __IO uint32_t PIO2_7; /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
+ __IO uint32_t PIO2_8; /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
+ __IO uint32_t PIO2_1; /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
+ __IO uint32_t PIO0_3; /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
+ __IO uint32_t PIO0_4; /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
+ __IO uint32_t PIO0_5; /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
+ __IO uint32_t PIO1_9; /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
+ __IO uint32_t PIO3_4; /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
+
+ __IO uint32_t PIO2_4; /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
+ __IO uint32_t PIO2_5; /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
+ __IO uint32_t PIO3_5; /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
+ __IO uint32_t PIO0_6; /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
+ __IO uint32_t PIO0_7; /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
+ __IO uint32_t PIO2_9; /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
+ __IO uint32_t PIO2_10; /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
+ __IO uint32_t PIO2_2; /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
+
+ __IO uint32_t PIO0_8; /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
+ __IO uint32_t PIO0_9; /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
+ __IO uint32_t JTAG_TCK_PIO0_10; /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
+ __IO uint32_t PIO1_10; /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
+ __IO uint32_t PIO2_11; /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
+ __IO uint32_t JTAG_TDI_PIO0_11; /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
+ __IO uint32_t JTAG_TMS_PIO1_0; /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
+ __IO uint32_t JTAG_TDO_PIO1_1; /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
+
+ __IO uint32_t JTAG_nTRST_PIO1_2; /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
+ __IO uint32_t PIO3_0; /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
+ __IO uint32_t PIO3_1; /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
+ __IO uint32_t PIO2_3; /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
+ __IO uint32_t ARM_SWDIO_PIO1_3; /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
+ __IO uint32_t PIO1_4; /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
+ __IO uint32_t PIO1_11; /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
+ __IO uint32_t PIO3_2; /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
+
+ __IO uint32_t PIO1_5; /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
+ __IO uint32_t PIO1_6; /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
+ __IO uint32_t PIO1_7; /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
+ __IO uint32_t PIO3_3; /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
+ __IO uint32_t SCK_LOC; /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
+ __IO uint32_t DSR_LOC; /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
+ __IO uint32_t DCD_LOC; /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
+ __IO uint32_t RI_LOC; /*!< Offset: 0x0BC RI pin location Register (R/W) */
+} LPC_IOCON_TypeDef;
+/*@}*/ /* end of group LPC11xx_IOCON */
+
+
+/*------------- Power Management Unit (PMU) --------------------------*/
+/** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
+ __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
+ __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
+ __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
+ __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
+ __IO uint32_t GPREG4; /*!< Offset: 0x014 General purpose Register 4 (R/W) */
+} LPC_PMU_TypeDef;
+/*@}*/ /* end of group LPC11xx_PMU */
+
+
+/*------------- General Purpose Input/Output (GPIO) --------------------------*/
+/** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
+ @{
+*/
+typedef struct
+{
+ union {
+ __IO uint32_t MASKED_ACCESS[4096]; /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
+ struct {
+ uint32_t RESERVED0[4095];
+ __IO uint32_t DATA; /*!< Offset: 0x3FFC Port data Register (R/W) */
+ };
+ };
+ uint32_t RESERVED1[4096];
+ __IO uint32_t DIR; /*!< Offset: 0x8000 Data direction Register (R/W) */
+ __IO uint32_t IS; /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
+ __IO uint32_t IBE; /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
+ __IO uint32_t IEV; /*!< Offset: 0x800C Interrupt event Register (R/W) */
+ __IO uint32_t IE; /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
+ __IO uint32_t RIS; /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
+ __IO uint32_t MIS; /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
+ __IO uint32_t IC; /*!< Offset: 0x801C Interrupt clear Register (R/W) */
+} LPC_GPIO_TypeDef;
+/*@}*/ /* end of group LPC11xx_GPIO */
+
+
+/*------------- Timer (TMR) --------------------------------------------------*/
+/** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t IR; /*!< Offset: 0x000 Interrupt Register (R/W) */
+ __IO uint32_t TCR; /*!< Offset: 0x004 Timer Control Register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x008 Timer Counter Register (R/W) */
+ __IO uint32_t PR; /*!< Offset: 0x00C Prescale Register (R/W) */
+ __IO uint32_t PC; /*!< Offset: 0x010 Prescale Counter Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x014 Match Control Register (R/W) */
+ __IO uint32_t MR0; /*!< Offset: 0x018 Match Register 0 (R/W) */
+ __IO uint32_t MR1; /*!< Offset: 0x01C Match Register 1 (R/W) */
+ __IO uint32_t MR2; /*!< Offset: 0x020 Match Register 2 (R/W) */
+ __IO uint32_t MR3; /*!< Offset: 0x024 Match Register 3 (R/W) */
+ __IO uint32_t CCR; /*!< Offset: 0x028 Capture Control Register (R/W) */
+ __I uint32_t CR0; /*!< Offset: 0x02C Capture Register 0 (R/ ) */
+ uint32_t RESERVED1[3];
+ __IO uint32_t EMR; /*!< Offset: 0x03C External Match Register (R/W) */
+ uint32_t RESERVED2[12];
+ __IO uint32_t CTCR; /*!< Offset: 0x070 Count Control Register (R/W) */
+ __IO uint32_t PWMC; /*!< Offset: 0x074 PWM Control Register (R/W) */
+} LPC_TMR_TypeDef;
+/*@}*/ /* end of group LPC11xx_TMR */
+
+
+/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
+/** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
+ @{
+*/
+typedef struct
+{
+ union {
+ __I uint32_t RBR; /*!< Offset: 0x000 Receiver Buffer Register (R/ ) */
+ __O uint32_t THR; /*!< Offset: 0x000 Transmit Holding Register ( /W) */
+ __IO uint32_t DLL; /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
+ };
+ union {
+ __IO uint32_t DLM; /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
+ __IO uint32_t IER; /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
+ };
+ union {
+ __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
+ __O uint32_t FCR; /*!< Offset: 0x008 FIFO Control Register ( /W) */
+ };
+ __IO uint32_t LCR; /*!< Offset: 0x00C Line Control Register (R/W) */
+ __IO uint32_t MCR; /*!< Offset: 0x010 Modem control Register (R/W) */
+ __I uint32_t LSR; /*!< Offset: 0x014 Line Status Register (R/ ) */
+ __I uint32_t MSR; /*!< Offset: 0x018 Modem status Register (R/ ) */
+ __IO uint32_t SCR; /*!< Offset: 0x01C Scratch Pad Register (R/W) */
+ __IO uint32_t ACR; /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t FDR; /*!< Offset: 0x028 Fractional Divider Register (R/W) */
+ uint32_t RESERVED1;
+ __IO uint32_t TER; /*!< Offset: 0x030 Transmit Enable Register (R/W) */
+ uint32_t RESERVED2[6];
+ __IO uint32_t RS485CTRL; /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
+ __IO uint32_t ADRMATCH; /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
+ __IO uint32_t RS485DLY; /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
+ __I uint32_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register (R/ ) */
+} LPC_UART_TypeDef;
+/*@}*/ /* end of group LPC11xx_UART */
+
+
+/*------------- Synchronous Serial Communication (SSP) -----------------------*/
+/** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR0; /*!< Offset: 0x000 Control Register 0 (R/W) */
+ __IO uint32_t CR1; /*!< Offset: 0x004 Control Register 1 (R/W) */
+ __IO uint32_t DR; /*!< Offset: 0x008 Data Register (R/W) */
+ __I uint32_t SR; /*!< Offset: 0x00C Status Registe (R/ ) */
+ __IO uint32_t CPSR; /*!< Offset: 0x010 Clock Prescale Register (R/W) */
+ __IO uint32_t IMSC; /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
+ __IO uint32_t RIS; /*!< Offset: 0x018 Raw Interrupt Status Register (R/W) */
+ __IO uint32_t MIS; /*!< Offset: 0x01C Masked Interrupt Status Register (R/W) */
+ __IO uint32_t ICR; /*!< Offset: 0x020 SSPICR Interrupt Clear Register (R/W) */
+} LPC_SSP_TypeDef;
+/*@}*/ /* end of group LPC11xx_SSP */
+
+
+/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
+/** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CONSET; /*!< Offset: 0x000 I2C Control Set Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x004 I2C Status Register (R/ ) */
+ __IO uint32_t DAT; /*!< Offset: 0x008 I2C Data Register (R/W) */
+ __IO uint32_t ADR0; /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
+ __IO uint32_t SCLH; /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
+ __IO uint32_t SCLL; /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
+ __O uint32_t CONCLR; /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
+ __IO uint32_t MMCTRL; /*!< Offset: 0x01C Monitor mode control register (R/W) */
+ __IO uint32_t ADR1; /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
+ __IO uint32_t ADR2; /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
+ __IO uint32_t ADR3; /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
+ __I uint32_t DATA_BUFFER; /*!< Offset: 0x02C Data buffer register ( /W) */
+ __IO uint32_t MASK0; /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
+ __IO uint32_t MASK1; /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
+ __IO uint32_t MASK2; /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
+ __IO uint32_t MASK3; /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
+} LPC_I2C_TypeDef;
+/*@}*/ /* end of group LPC11xx_I2C */
+
+
+/*------------- Watchdog Timer (WDT) -----------------------------------------*/
+/** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
+ __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
+ __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register ( /W) */
+ __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R/ ) */
+} LPC_WDT_TypeDef;
+/*@}*/ /* end of group LPC11xx_WDT */
+
+
+/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
+/** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
+ @{
+*/
+typedef struct
+{
+ __IO uint32_t CR; /*!< Offset: 0x000 A/D Control Register (R/W) */
+ __IO uint32_t GDR; /*!< Offset: 0x004 A/D Global Data Register (R/W) */
+ uint32_t RESERVED0;
+ __IO uint32_t INTEN; /*!< Offset: 0x00C A/D Interrupt Enable Register (R/W) */
+ __IO uint32_t DR[8]; /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
+ __I uint32_t STAT; /*!< Offset: 0x030 A/D Status Register (R/ ) */
+} LPC_ADC_TypeDef;
+/*@}*/ /* end of group LPC11xx_ADC */
+
+
+#if defined ( __CC_ARM )
+#pragma no_anon_unions
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* Base addresses */
+#define LPC_FLASH_BASE (0x00000000UL)
+#define LPC_RAM_BASE (0x10000000UL)
+#define LPC_APB0_BASE (0x40000000UL)
+#define LPC_AHB_BASE (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
+#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
+#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
+#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
+#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
+#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
+#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
+#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
+#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
+#define LPC_SSP0_BASE (LPC_APB0_BASE + 0x40000)
+#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
+#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
+#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x58000)
+
+/* AHB peripherals */
+#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
+#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
+#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
+#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
+#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
+#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
+#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
+#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
+#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
+#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
+#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
+#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
+#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
+#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
+#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
+#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
+#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
+#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
+#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
+#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __LPC11xx_H__ */
diff --git a/os/hal/platforms/LPC11xx/hal_lld.c b/os/hal/platforms/LPC11xx/hal_lld.c new file mode 100644 index 000000000..976fed23b --- /dev/null +++ b/os/hal/platforms/LPC11xx/hal_lld.c @@ -0,0 +1,132 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC111x/hal_lld.c
+ * @brief LPC111x HAL subsystem low level driver source.
+ *
+ * @addtogroup LPC111x_HAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief Register missing in NXP header file. + */
+#define FLASHCFG (*((volatile uint32_t *)0x4003C010))
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ */
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level HAL driver initialization.
+ */
+void hal_lld_init(void) {
+
+ /* SysTick initialization using the system clock.*/
+ NVICSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK);
+ SysTick->LOAD = LPC11xx_SYSCLK / CH_FREQUENCY - 1;
+ SysTick->VAL = 0;
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_ENABLE_Msk |
+ SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+ * @brief LPC111x clocks and PLL initialization.
+ * @note All the involved constants come from the file @p board.h.
+ */
+void lpc111x_clock_init(void) {
+ unsigned i;
+
+ /* Flash wait states setting, the code takes care to not touch TBD bits.*/
+ FLASHCFG = (FLASHCFG & ~3) | LPC11xx_FLASHCFG_FLASHTIM;
+
+ /* System oscillator initialization if required.*/
+#if LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
+#if LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC
+ LPC_SYSCON->SYSOSCCTRL = LPC11xx_SYSOSCCTRL;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* System oscillator ON. */
+ for (i = 0; i < 200; i++)
+ __NOP(); /* Stabilization delay. */
+#endif /* LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC */
+
+ /* PLL initialization if required.*/
+ LPC_SYSCON->SYSPLLCLKSEL = LPC11xx_PLLCLK_SOURCE;
+ LPC_SYSCON->SYSPLLCLKUEN = 1; /* Really required? */
+ LPC_SYSCON->SYSPLLCLKUEN = 0;
+ LPC_SYSCON->SYSPLLCLKUEN = 1;
+ LPC_SYSCON->SYSPLLCTRL = LPC11xx_SYSPLLCTRL_MSEL | LPC11xx_SYSPLLCTRL_PSEL;
+ LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* System PLL ON. */
+ while ((LPC_SYSCON->SYSPLLSTAT & 1) == 0) /* Wait PLL lock. */
+ ;
+#endif /* LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT */
+
+ /* Main clock source selection.*/
+ LPC_SYSCON->MAINCLKSEL = LPC11xx_MAINCLK_SOURCE;
+ LPC_SYSCON->MAINCLKUEN = 1; /* Really required? */
+ LPC_SYSCON->MAINCLKUEN = 0;
+ LPC_SYSCON->MAINCLKUEN = 1;
+ while ((LPC_SYSCON->MAINCLKUEN & 1) == 0) /* Wait switch completion. */
+ ;
+
+ /* ABH divider initialization, peripheral clocks are initially disabled,
+ the various device drivers will handle their own setup except GPIO and
+ IOCON that are left enabled.*/
+ LPC_SYSCON->SYSAHBCLKDIV = LPC11xx_SYSABHCLK_DIV;
+ LPC_SYSCON->SYSAHBCLKCTRL = 0x0001005F;
+
+ /* Peripheral clock dividers initialization.*/
+ LPC_SYSCON->UARTCLKDIV = LPC11xx_UART_PCLK_DIV;
+
+ /* Memory remapping, vectors always in ROM.*/
+ LPC_SYSCON->SYSMEMREMAP = 2;
+}
+
+/** @} */
diff --git a/os/hal/platforms/LPC11xx/hal_lld.h b/os/hal/platforms/LPC11xx/hal_lld.h new file mode 100644 index 000000000..523eb0a6f --- /dev/null +++ b/os/hal/platforms/LPC11xx/hal_lld.h @@ -0,0 +1,231 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC111x/hal_lld.h
+ * @brief HAL subsystem low level driver header template.
+ *
+ * @addtogroup LPC111x_HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "LPC11xx.h"
+#include "nvic.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Platform name.
+ */
+#define PLATFORM_NAME "LPC111x"
+
+#define IRCOSCCLK 12000000 /**< High speed internal clock. */
+#define WDGOSCCLK 1600000 /**< Watchdog internal clock. */
+
+#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator
+ clock source. */
+#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock
+ source. */
+
+#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */
+#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */
+#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */
+#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief System PLL clock source.
+ */
+#if !defined(LPC11xx_PLLCLK_SOURCE) || defined(__DOXYGEN__)
+#define LPC11xx_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC
+#endif
+
+/**
+ * @brief System PLL multiplier.
+ * @note The value must be in the 1..32 range and the final frequency
+ * must not exceed the CCO ratings.
+ */
+#if !defined(LPC11xx_SYSPLL_MUL) || defined(__DOXYGEN__)
+#define LPC11xx_SYSPLL_MUL 4
+#endif
+
+/**
+ * @brief System PLL divider.
+ * @note The value must be chosen between (2, 4, 8, 16).
+ */
+#if !defined(LPC11xx_SYSPLL_DIV) || defined(__DOXYGEN__)
+#define LPC11xx_SYSPLL_DIV 4
+#endif
+
+/**
+ * @brief System main clock source.
+ */
+#if !defined(LPC11xx_MAINCLK_SOURCE) || defined(__DOXYGEN__)
+#define LPC11xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT
+#endif
+
+/**
+ * @brief AHB clock divider.
+ * @note The value must be chosen between (1...255).
+ */
+#if !defined(LPC11xx_SYSCLK_DIV) || defined(__DOXYGEN__)
+#define LPC11xx_SYSABHCLK_DIV 1
+#endif
+
+/**
+ * @brief UART clock divider.
+ * @note The value must be chosen between (1...255).
+ */
+#if !defined(LPC11xx_UART_PCLK_DIV) || defined(__DOXYGEN__)
+#define LPC11xx_UART_PCLK_DIV 1
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/**
+ * @brief Calculated SYSOSCCTRL setting. + */
+#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__)
+#define LPC11xx_SYSOSCCTRL 0
+#else
+#define LPC11xx_SYSOSCCTRL 1
+#endif
+
+/**
+ * @brief PLL input clock frequency. + */
+#if (LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__)
+#define LPC11xx_SYSPLLCLKIN SYSOSCCLK
+#elif LPC11xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOCS
+#define LPC11xx_SYSPLLCLKIN IRCOSCCLK
+#else
+#error "invalid LPC11xx_PLLCLK_SOURCE clock source specified"
+#endif
+
+/**
+ * @brief MSEL mask in SYSPLLCTRL register.
+ */
+#if (LPC11xx_SYSPLL_MUL >= 1) && (LPC11xx_SYSPLL_MUL <= 32) || \
+ defined(__DOXYGEN__)
+#define LPC11xx_SYSPLLCTRL_MSEL (LPC11xx_SYSPLL_MUL - 1)
+#else
+#error "LPC11xx_SYSPLL_MUL out of range (1...32)"
+#endif
+
+/**
+ * @brief PSEL mask in SYSPLLCTRL register. + */
+#if (LPC11xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__)
+#define LPC11xx_SYSPLLCTRL_PSEL (0 << 5)
+#elif LPC11xx_SYSPLL_DIV == 4
+#define LPC11xx_SYSPLLCTRL_PSEL (1 << 5)
+#elif LPC11xx_SYSPLL_DIV == 8
+#define LPC11xx_SYSPLLCTRL_PSEL (2 << 5)
+#elif LPC11xx_SYSPLL_DIV == 16
+#define LPC11xx_SYSPLLCTRL_PSEL (3 << 5)
+#else
+#error "invalid LPC11xx_SYSPLL_DIV value (2,4,8,16)"
+#endif
+
+/**
+ * @brief CCP frequency. + */
+#define LPC11xx_SYSPLLCCO (LPC11xx_SYSPLLCLKIN * LPC11xx_SYSPLL_MUL * \
+ LPC11xx_SYSPLL_DIV)
+
+#if (LPC11xx_SYSPLLCCO < 156000000) || (LPC11xx_SYSPLLCCO > 320000000)
+#error "CCO frequency out of the acceptable range (156...320)"
+#endif
+
+/**
+ * @brief PLL output clock frequency.
+ */
+#define LPC11xx_SYSPLLCLKOUT (LPC11xx_SYSPLLCCO / LPC11xx_SYSPLL_DIV)
+
+#if (LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOCS) || defined(__DOXYGEN__)
+#define LPC11xx_MAINCLK IRCOSCCLK
+#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN
+#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKIN
+#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC
+#define LPC11xx_MAINCLK WDGOSCCLK
+#elif LPC11xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT
+#define LPC11xx_MAINCLK LPC11xx_SYSPLLCLKOUT
+#else
+#error "invalid LPC11xx_MAINCLK_SOURCE clock source specified"
+#endif
+
+/**
+ * @brief AHB clock.
+ */
+#if (LPC11xx_SYSCLK <= 50000000) || defined(__DOXYGEN__)
+#define LPC11xx_SYSCLK (LPC11xx_MAINCLK / LPC11xx_SYSABHCLK_DIV)
+#else
+#error "AHB clock frequency out of the acceptable range (50MHz max)"
+#endif
+
+/**
+ * @brief Flash wait states. + */
+#if (LPC11xx_SYSCLK <= 20000000) || defined(__DOXYGEN__)
+#define LPC11xx_FLASHCFG_FLASHTIM 0
+#elif LPC11xx_SYSCLK <= 40000000
+#define LPC11xx_FLASHCFG_FLASHTIM 1
+#else
+#define LPC11xx_FLASHCFG_FLASHTIM 2
+#endif
+
+/**
+ * @brief UART clock.
+ */
+#define LPC11xx_UART_PCLK (LPC11xx_MAINCLK / LPC11xx_UART_PCLK_DIV)
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hal_lld_init(void);
+ void lpc111x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/LPC11xx/pal_lld.c b/os/hal/platforms/LPC11xx/pal_lld.c new file mode 100644 index 000000000..2054cd271 --- /dev/null +++ b/os/hal/platforms/LPC11xx/pal_lld.c @@ -0,0 +1,95 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC111x/pal_lld.c
+ * @brief LPC111x GPIO low level driver code.
+ *
+ * @addtogroup LPC111x_PAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if CH_HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+/**
+ * @brief LPC111x I/O ports configuration.
+ * @details GPIO unit registers initialization.
+ *
+ * @param[in] config the LPC111x ports configuration
+ */
+void _pal_lld_init(const PALConfig *config) {
+
+ LPC_GPIO0->DIR = config->P0.dir;
+ LPC_GPIO1->DIR = config->P1.dir;
+ LPC_GPIO2->DIR = config->P2.dir;
+ LPC_GPIO3->DIR = config->P3.dir;
+ LPC_GPIO0->DATA = config->P0.data;
+ LPC_GPIO1->DATA = config->P1.data;
+ LPC_GPIO2->DATA = config->P2.data;
+ LPC_GPIO3->DATA = config->P3.data;
+}
+
+/**
+ * @brief Pads mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ *
+ * @param[in] port the port identifier
+ * @param[in] mask the group mask
+ * @param[in] mode the mode
+ *
+ * @note This function is not meant to be invoked directly by the application
+ * code.
+ * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with high
+ * state.
+ * @note This function does not alter the @p PINSELx registers. Alternate
+ * functions setup must be handled by device-specific code.
+ */
+void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t mode) {
+
+ (void)port; (void)mask; (void)mode;
+}
+
+#endif /* CH_HAL_USE_PAL */
+
+/** @} */
diff --git a/os/hal/platforms/LPC11xx/pal_lld.h b/os/hal/platforms/LPC11xx/pal_lld.h new file mode 100644 index 000000000..8b871721d --- /dev/null +++ b/os/hal/platforms/LPC11xx/pal_lld.h @@ -0,0 +1,309 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC111x/pal_lld.h
+ * @brief LPC111x GPIO low level driver header.
+ *
+ * @addtogroup LPC111x_PAL
+ * @{
+ */
+
+#ifndef _PAL_LLD_H_
+#define _PAL_LLD_H_
+
+#if CH_HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Unsupported modes and specific modes */
+/*===========================================================================*/
+
+#undef PAL_MODE_INPUT_PULLUP
+#undef PAL_MODE_INPUT_PULLDOWN
+#undef PAL_MODE_INPUT_ANALOG
+#undef PAL_MODE_OUTPUT_OPENDRAIN
+
+/*===========================================================================*/
+/* I/O Ports Types and constants. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIO port setup info.
+ */
+typedef struct {
+ /** Initial value for FIO_PIN register.*/
+ uint32_t data;
+ /** Initial value for FIO_DIR register.*/
+ uint32_t dir;
+} lpc111x_gpio_setup_t;
+
+/**
+ * @brief GPIO static initializer.
+ * @details An instance of this structure must be passed to @p palInit() at
+ * system startup time in order to initialized the digital I/O
+ * subsystem. This represents only the initial setup, specific pads
+ * or whole ports can be reprogrammed at later time.
+ * @note The @p IOCON block is not configured, initially all pins have
+ * enabled pullups and are programmed as GPIO. It is responsibility
+ * of the various drivers to reprogram the pins in the proper mode.
+ * Pins that are not handled by any driver may be programmed in
+ * @p board.c.
+ */
+typedef struct {
+ /** @brief GPIO 0 setup data.*/
+ lpc111x_gpio_setup_t P0;
+ /** @brief GPIO 1 setup data.*/
+ lpc111x_gpio_setup_t P1;
+ /** @brief GPIO 2 setup data.*/
+ lpc111x_gpio_setup_t P2;
+ /** @brief GPIO 3 setup data.*/
+ lpc111x_gpio_setup_t P3;
+} PALConfig;
+
+/**
+ * @brief Width, in bits, of an I/O port.
+ */
+#define PAL_IOPORTS_WIDTH 32
+
+/**
+ * @brief Whole port mask.
+ * @brief This macro specifies all the valid bits into a port.
+ */
+#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF)
+
+/**
+ * @brief Digital I/O port sized unsigned type.
+ */
+typedef uint32_t ioportmask_t;
+
+/**
+ * @brief Port Identifier.
+ */
+typedef LPC_GPIO_TypeDef *ioportid_t;
+
+/*===========================================================================*/
+/* I/O Ports Identifiers. */
+/*===========================================================================*/
+
+/**
+ * @brief GPIO0 port identifier.
+ */
+#define IOPORT1 LPC_GPIO0
+#define GPIO0 LPC_GPIO0
+
+/**
+ * @brief GPIO1 port identifier.
+ */
+#define IOPORT2 LPC_GPIO1
+#define GPIO1 LPC_GPIO1
+
+/**
+ * @brief GPIO2 port identifier.
+ */
+#define IOPORT3 LPC_GPIO2
+#define GPIO2 LPC_GPIO2
+
+/**
+ * @brief GPIO3 port identifier.
+ */
+#define IOPORT4 LPC_GPIO3
+#define GPIO3 LPC_GPIO3
+
+/*===========================================================================*/
+/* Implementation, some of the following macros could be implemented as */
+/* functions, if so please put them in pal_lld.c. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level PAL subsystem initialization.
+ *
+ * @param[in] config architecture-dependent ports configuration
+ */
+#define pal_lld_init(config) _pal_lld_init(config)
+
+/**
+ * @brief Reads the physical I/O port states.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ *
+ * @param[in] port port identifier
+ * @return The port bits.
+ */
+#define pal_lld_readport(port) ((port)->DATA)
+
+/**
+ * @brief Reads the output latch.
+ * @details The purpose of this function is to read back the latched output
+ * value.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ *
+ * @param[in] port port identifier
+ * @return The latched logical states.
+ */
+#define pal_lld_readlatch(port) ((port)->DATA)
+
+/**
+ * @brief Writes a bits mask on a I/O port.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be written on the specified port
+ */
+#define pal_lld_writeport(port, bits) ((port)->DATA = (bits))
+
+/**
+ * @brief Sets a bits mask on a I/O port.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be ORed on the specified port
+ */
+#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFFFFFFFF)
+
+/**
+ * @brief Clears a bits mask on a I/O port.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] bits bits to be cleared on the specified port
+ */
+#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0)
+
+/**
+ * @brief Reads a group of bits.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @return The group logical states.
+ */
+#define pal_lld_readgroup(port, mask, offset) \
+ ((port)->MASKED_ACCESS[(mask) << (offset)])
+
+/**
+ * @brief Writes a group of bits.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] offset group bit offset within the port
+ * @param[in] bits bits to be written. Values exceeding the group width
+ * are masked.
+ */
+#define pal_lld_writegroup(port, mask, offset, bits) \
+ ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits))
+
+/**
+ * @brief Pads group mode setup.
+ * @details This function programs a pads group belonging to the same port
+ * with the specified mode.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port port identifier
+ * @param[in] mask group mask
+ * @param[in] mode group mode
+ */
+#define pal_lld_setgroupmode(port, mask, mode) \
+ _pal_lld_setgroupmode(port, mask, mode)
+
+/**
+ * @brief Writes a logical state on an output pad.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ * @param[out] bit logical value, the value must be @p PAL_LOW or
+ * @p PAL_HIGH
+ */
+#define pal_lld_writepad(port, pad, bit) \
+ ((port)->MASKED_ACCESS[(mask) << (pad)] = (bit) << (pad))
+
+/**
+ * @brief Sets a pad logical state to @p PAL_HIGH.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ */
+#define pal_lld_setpad(port, pad) \
+ ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad))
+
+/**
+ * @brief Clears a pad logical state to @p PAL_LOW.
+ * @note This function is not meant to be invoked directly by the
+ * application code.
+ * @note The @ref PAL provides a default software implementation of this
+ * functionality, implement this function if can optimize it by using
+ * special hardware functionalities or special coding.
+ *
+ * @param[in] port port identifier
+ * @param[in] pad pad number within the port
+ */
+#define pal_lld_clearpad(port, pad) \
+ ((port)->MASKED_ACCESS[1 << (pad)] = 0)
+
+#if !defined(__DOXYGEN__)
+extern const PALConfig pal_default_config;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _pal_lld_init(const PALConfig *config);
+ void _pal_lld_setgroupmode(ioportid_t port,
+ ioportmask_t mask,
+ uint_fast8_t mode);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CH_HAL_USE_PAL */
+
+#endif /* _PAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/LPC11xx/platform.dox b/os/hal/platforms/LPC11xx/platform.dox new file mode 100644 index 000000000..11df786db --- /dev/null +++ b/os/hal/platforms/LPC11xx/platform.dox @@ -0,0 +1,76 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @defgroup LPC111x LPC111x Support
+ * @brief LPC111x specific support.
+ * @details The LPC111x support includes:
+ * - I/O ports driver.
+ * - Buffered, interrupt driven, serial driver.
+ * - A demo supporting the kernel test suite.
+ * .
+ * @ingroup ARMCMx
+ */
+
+/**
+ * @defgroup LPC111x_HAL LPC111x HAL Support
+ * @brief HAL support.
+ *
+ * @ingroup LPC111x
+ */
+
+/**
+ * @defgroup LPC111x_PAL LPC111x I/O Ports Support
+ * @brief I/O Ports peripherals support.
+ * @details This module supports the LPC111x GPIO controller. The controller
+ * supports the following features (see @ref PAL):
+ * - 12 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * <h2>Supported Setup Modes</h2>
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * <h2>Suboptimal Behavior</h2>
+ * Some GPIO features are less than optimal:
+ * - Pad/port toggling operations are not atomic.
+ * - Pull-up and Pull-down resistors cannot be programmed through the PAL
+ * driver and must be programmed separately.
+ * - Reading of the output latch for pads programmed as input is not possible,
+ * the input pin value is returned instead.
+ * .
+ * @ingroup LPC111x
+ */
+
+/**
+ * @defgroup LPC111x_SERIAL LPC111x UART Support
+ * @brief UART peripherals support.
+ * @details The serial driver supports the LPC111x UART taking advantage of
+ * its deep hardware buffers.
+ *
+ * @ingroup LPC111x
+ */
diff --git a/os/hal/platforms/LPC11xx/platform.mk b/os/hal/platforms/LPC11xx/platform.mk new file mode 100644 index 000000000..99b6a10ba --- /dev/null +++ b/os/hal/platforms/LPC11xx/platform.mk @@ -0,0 +1,7 @@ +# List of all the LPC111x platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC111x/hal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/LPC111x/pal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/LPC111x/serial_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC111x
diff --git a/os/hal/platforms/LPC11xx/serial_lld.c b/os/hal/platforms/LPC11xx/serial_lld.c new file mode 100644 index 000000000..e77a47bb2 --- /dev/null +++ b/os/hal/platforms/LPC11xx/serial_lld.c @@ -0,0 +1,286 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC111x/serial_lld.c
+ * @brief LPC111x low level serial driver code.
+ *
+ * @addtogroup LPC111x_SERIAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+#if USE_LPC111x_UART0 || defined(__DOXYGEN__)
+/** @brief UART0 serial driver identifier.*/
+SerialDriver SD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/** @brief Driver default configuration.*/
+static const SerialConfig default_config = {
+ SERIAL_DEFAULT_BITRATE,
+ LCR_WL8 | LCR_STOP1 | LCR_NOPARITY,
+ FCR_TRIGGER0
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/**
+ * @brief UART initialization.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void uart_init(SerialDriver *sdp) {
+ LPC_UART_TypeDef *u = sdp->uart;
+
+ uint32_t div = LPC11xx_UART_PCLK / (sdp->config->sc_speed << 4);
+ u->LCR = sdp->config->sc_lcr | LCR_DLAB;
+ u->DLL = div;
+ u->DLM = div >> 8;
+ u->LCR = sdp->config->sc_lcr;
+ u->FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | sdp->config->sc_fcr;
+ u->ACR = 0;
+ u->FDR = 0x10;
+ u->TER = TER_ENABLE;
+ u->IER = IER_RBR | IER_STATUS;
+}
+
+/**
+ * @brief UART de-initialization.
+ *
+ * @param[in] u pointer to an UART I/O block
+ */
+static void uart_deinit(LPC_UART_TypeDef *u) {
+
+ u->LCR = LCR_DLAB;
+ u->DLL = 1;
+ u->DLM = 0;
+ u->LCR = 0;
+ u->FDR = 0x10;
+ u->IER = 0;
+ u->FCR = FCR_RXRESET | FCR_TXRESET;
+ u->ACR = 0;
+ u->TER = TER_ENABLE;
+}
+
+/**
+ * @brief Error handling routine.
+ *
+ * @param[in] sdp communication channel associated to the UART
+ * @param[in] err UART LSR register value
+ */
+static void set_error(SerialDriver *sdp, IOREG32 err) {
+ sdflags_t sts = 0;
+
+ if (err & LSR_OVERRUN)
+ sts |= SD_OVERRUN_ERROR;
+ if (err & LSR_PARITY)
+ sts |= SD_PARITY_ERROR;
+ if (err & LSR_FRAMING)
+ sts |= SD_FRAMING_ERROR;
+ if (err & LSR_BREAK)
+ sts |= SD_BREAK_DETECTED;
+ chSysLockFromIsr();
+ sdAddFlagsI(sdp, sts);
+ chSysUnlockFromIsr();
+}
+
+/**
+ * @brief Common IRQ handler.
+ * @note Tries hard to clear all the pending interrupt sources, we don't
+ * want to go through the whole ISR and have another interrupt soon
+ * after.
+ *
+ * @param[in] u pointer to an UART I/O block
+ * @param[in] sdp communication channel associated to the UART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+ LPC_UART_TypeDef *u = sdp->uart;
+
+ while (TRUE) {
+ switch (u->IIR & IIR_SRC_MASK) {
+ case IIR_SRC_NONE:
+ return;
+ case IIR_SRC_ERROR:
+ set_error(sdp, u->LSR);
+ break;
+ case IIR_SRC_TIMEOUT:
+ case IIR_SRC_RX:
+ chSysLockFromIsr();
+ if (chIQIsEmpty(&sdp->iqueue))
+ chEvtBroadcastI(&sdp->ievent);
+ chSysUnlockFromIsr();
+ while (u->LSR & LSR_RBR_FULL) {
+ chSysLockFromIsr();
+ if (chIQPutI(&sdp->iqueue, u->RBR) < Q_OK)
+ sdAddFlagsI(sdp, SD_OVERRUN_ERROR);
+ chSysUnlockFromIsr();
+ }
+ break;
+ case IIR_SRC_TX:
+ {
+ int i = LPC111x_UART_FIFO_PRELOAD;
+ do {
+ msg_t b;
+
+ chSysLockFromIsr();
+ b = chOQGetI(&sdp->oqueue);
+ chSysUnlockFromIsr();
+ if (b < Q_OK) {
+ u->IER &= ~IER_THRE;
+ chSysLockFromIsr();
+ chEvtBroadcastI(&sdp->oevent);
+ chSysUnlockFromIsr();
+ break;
+ }
+ u->THR = b;
+ } while (--i);
+ }
+ break;
+ default:
+ (void) u->THR;
+ (void) u->RBR;
+ }
+ }
+}
+
+/**
+ * @brief Attempts a TX FIFO preload.
+ */
+static void preload(SerialDriver *sdp) {
+ LPC_UART_TypeDef *u = sdp->uart;
+
+ if (u->LSR & LSR_THRE) {
+ int i = LPC111x_UART_FIFO_PRELOAD;
+ do {
+ msg_t b = chOQGetI(&sdp->oqueue);
+ if (b < Q_OK) {
+ chEvtBroadcastI(&sdp->oevent);
+ return;
+ }
+ u->THR = b;
+ } while (--i);
+ }
+ u->IER |= IER_THRE;
+}
+
+/**
+ * @brief Driver SD1 output notification.
+ */
+#if USE_LPC111x_UART0 || defined(__DOXYGEN__)
+static void notify1(void) {
+
+ preload(&SD1);
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/**
+ * @brief UART0 IRQ handler.
+ */
+#if USE_LPC111x_UART0 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(Vector94) {
+
+ CH_IRQ_PROLOGUE();
+
+ serve_interrupt(&SD1);
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level serial driver initialization.
+ */
+void sd_lld_init(void) {
+
+#if USE_LPC111x_UART0
+ sdObjectInit(&SD1, NULL, notify1);
+ SD1.uart = LPC_UART;
+ LPC_IOCON->PIO1_6 = 0xC1; /* RDX without resistors. */
+ LPC_IOCON->PIO1_7 = 0xC1; /* TDX without resistors. */
+#endif
+}
+
+/**
+ * @brief Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ */
+void sd_lld_start(SerialDriver *sdp) {
+
+ if (sdp->config == NULL)
+ sdp->config = &default_config;
+
+ if (sdp->state == SD_STOP) {
+#if USE_LPC111x_UART0
+ if (&SD1 == sdp) {
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 12);
+ NVICEnableVector(UART_IRQn,
+ CORTEX_PRIORITY_MASK(LPC111x_UART0_PRIORITY));
+ }
+#endif
+ }
+ uart_init(sdp);
+}
+
+/**
+ * @brief Low level serial driver stop.
+ * @details De-initializes the UART, stops the associated clock, resets the
+ * interrupt vector.
+ *
+ * @param[in] sdp pointer to a @p SerialDriver object
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+ if (sdp->state == SD_READY) {
+ uart_deinit(sdp->uart);
+#if USE_LPC111x_UART0
+ if (&SD1 == sdp) {
+ LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 12);
+ NVICDisableVector(UART_IRQn);
+ return;
+ }
+#endif
+ }
+}
+
+#endif /* CH_HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/platforms/LPC11xx/serial_lld.h b/os/hal/platforms/LPC11xx/serial_lld.h new file mode 100644 index 000000000..f67c5404f --- /dev/null +++ b/os/hal/platforms/LPC11xx/serial_lld.h @@ -0,0 +1,203 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file LPC111x/serial_lld.h
+ * @brief LPC111x low level serial driver header.
+ *
+ * @addtogroup LPC111x_SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define IIR_SRC_MASK 0x0F
+#define IIR_SRC_NONE 0x01
+#define IIR_SRC_MODEM 0x00
+#define IIR_SRC_TX 0x02
+#define IIR_SRC_RX 0x04
+#define IIR_SRC_ERROR 0x06
+#define IIR_SRC_TIMEOUT 0x0C
+
+#define IER_RBR 1
+#define IER_THRE 2
+#define IER_STATUS 4
+
+#define LCR_WL5 0
+#define LCR_WL6 1
+#define LCR_WL7 2
+#define LCR_WL8 3
+#define LCR_STOP1 0
+#define LCR_STOP2 4
+#define LCR_NOPARITY 0
+#define LCR_PARITYODD 0x08
+#define LCR_PARITYEVEN 0x18
+#define LCR_PARITYONE 0x28
+#define LCR_PARITYZERO 0x38
+#define LCR_BREAK_ON 0x40
+#define LCR_DLAB 0x80
+
+#define FCR_ENABLE 1
+#define FCR_RXRESET 2
+#define FCR_TXRESET 4
+#define FCR_TRIGGER0 0
+#define FCR_TRIGGER1 0x40
+#define FCR_TRIGGER2 0x80
+#define FCR_TRIGGER3 0xC0
+
+#define LSR_RBR_FULL 1
+#define LSR_OVERRUN 2
+#define LSR_PARITY 4
+#define LSR_FRAMING 8
+#define LSR_BREAK 0x10
+#define LSR_THRE 0x20
+#define LSR_TEMT 0x40
+#define LSR_RXFE 0x80
+
+#define TER_ENABLE 0x80
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief UART0 driver enable switch.
+ * @details If set to @p TRUE the support for UART0 is included.
+ * @note The default is @p TRUE .
+ */
+#if !defined(USE_LPC111x_UART0) || defined(__DOXYGEN__)
+#define USE_LPC111x_UART0 TRUE
+#endif
+
+/**
+ * @brief FIFO preload parameter.
+ * @details Configuration parameter, this values defines how many bytes are
+ * preloaded in the HW transmit FIFO for each interrupt, the maximum value is
+ * 16 the minimum is 1.
+ * @note An high value reduces the number of interrupts generated but can
+ * also increase the worst case interrupt response time because the
+ * preload loops.
+ */
+#if !defined(LPC111x_UART_FIFO_PRELOAD) || defined(__DOXYGEN__)
+#define LPC111x_UART_FIFO_PRELOAD 16
+#endif
+
+/**
+ * @brief UART0 interrupt priority level setting.
+ */
+#if !defined(LPC111x_UART0_PRIORITY) || defined(__DOXYGEN__)
+#define LPC111x_UART0_PRIORITY 3
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if (LPC111x_UART_FIFO_PRELOAD < 1) || (LPC111x_UART_FIFO_PRELOAD > 16)
+#error "invalid LPC214x_UART_FIFO_PRELOAD setting"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Serial Driver condition flags type.
+ */
+typedef uint32_t sdflags_t;
+
+/**
+ * @brief LPC214x Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ * in order to configure and start a serial driver operations.
+ */
+typedef struct {
+ /**
+ * @brief Bit rate.
+ */
+ uint32_t sc_speed;
+ /**
+ * @brief Initialization value for the LCR register.
+ */
+ uint32_t sc_lcr;
+ /**
+ * @brief Initialization value for the FCR register.
+ */
+ uint32_t sc_fcr;
+} SerialConfig;
+
+/**
+ * @brief @p SerialDriver specific data.
+ */
+#define _serial_driver_data \
+ _base_asynchronous_channel_data \
+ /* Driver state.*/ \
+ sdstate_t state; \
+ /* Current configuration data.*/ \
+ const SerialConfig *config; \
+ /* Input queue.*/ \
+ InputQueue iqueue; \
+ /* Output queue.*/ \
+ OutputQueue oqueue; \
+ /* Status Change @p EventSource.*/ \
+ EventSource sevent; \
+ /* I/O driver status flags.*/ \
+ sdflags_t flags; \
+ /* Input circular buffer.*/ \
+ uint8_t ib[SERIAL_BUFFERS_SIZE]; \
+ /* Output circular buffer.*/ \
+ uint8_t ob[SERIAL_BUFFERS_SIZE]; \
+ /* End of the mandatory fields.*/ \
+ /* Pointer to the USART registers block.*/ \
+ LPC_UART_TypeDef *uart;
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if USE_LPC111x_UART0 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sd_lld_init(void);
+ void sd_lld_start(SerialDriver *sdp);
+ void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CH_HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/LPC11xx/system_LPC11xx.h b/os/hal/platforms/LPC11xx/system_LPC11xx.h new file mode 100644 index 000000000..385fe3888 --- /dev/null +++ b/os/hal/platforms/LPC11xx/system_LPC11xx.h @@ -0,0 +1,64 @@ +/**************************************************************************//**
+ * @file system_LPC11xx.h
+ * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File
+ * for the NXP LPC11xx Device Series
+ * @version V1.00
+ * @date 17. November 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef __SYSTEM_LPC11xx_H
+#define __SYSTEM_LPC11xx_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * Initialize the system
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Setup the microcontroller system.
+ * Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param none
+ * @return none
+ *
+ * @brief Updates the SystemCoreClock with current core Clock
+ * retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSTEM_LPC11x_H */
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