aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--xen/arch/arm/arm32/head.S2
-rw-r--r--xen/arch/arm/arm64/head.S2
2 files changed, 2 insertions, 2 deletions
diff --git a/xen/arch/arm/arm32/head.S b/xen/arch/arm/arm32/head.S
index db3baa0c25..f2f581da97 100644
--- a/xen/arch/arm/arm32/head.S
+++ b/xen/arch/arm/arm32/head.S
@@ -189,7 +189,7 @@ skip_bss:
/* Set up the HTCR:
* PT walks use Outer-Shareable accesses,
- * PT walks are write-back, no-write-allocate in both cache levels,
+ * PT walks are write-back, write-allocate in both cache levels,
* Full 32-bit address space goes through this table. */
ldr r0, =0x80002500
mcr CP32(r0, HTCR)
diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
index b7ab251385..bbde419d5e 100644
--- a/xen/arch/arm/arm64/head.S
+++ b/xen/arch/arm/arm64/head.S
@@ -173,7 +173,7 @@ skip_bss:
* PASize -- 4G
* Top byte is used
* PT walks use Outer-Shareable accesses,
- * PT walks are write-back, no-write-allocate in both cache levels,
+ * PT walks are write-back, write-allocate in both cache levels,
* Full 64-bit address space goes through this table. */
ldr x0, =0x80802500
msr tcr_el2, x0